{"title":"根据组合逻辑块的功能描述估计测试集的相对单卡故障覆盖率","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/HLDVT.2001.972804","DOIUrl":null,"url":null,"abstract":"When the gate-level description of a logic block is unknown, it may become necessary to estimate the gate-level stuck-at fault coverage of a test set for the block by using a fault coverage metric that does not require simulation of gate-level faults. We propose such a metric based on stuck-at faults on primary inputs of the block We show that the proposed metric is accurate in predicting the relative gate-level stuck-at fault coverage of different test sets.","PeriodicalId":188469,"journal":{"name":"Sixth IEEE International High-Level Design Validation and Test Workshop","volume":"75 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Estimating the relative single stuck-at fault coverage of test sets for a combinational logic block from its functional description\",\"authors\":\"I. Pomeranz, S. Reddy\",\"doi\":\"10.1109/HLDVT.2001.972804\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"When the gate-level description of a logic block is unknown, it may become necessary to estimate the gate-level stuck-at fault coverage of a test set for the block by using a fault coverage metric that does not require simulation of gate-level faults. We propose such a metric based on stuck-at faults on primary inputs of the block We show that the proposed metric is accurate in predicting the relative gate-level stuck-at fault coverage of different test sets.\",\"PeriodicalId\":188469,\"journal\":{\"name\":\"Sixth IEEE International High-Level Design Validation and Test Workshop\",\"volume\":\"75 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-12-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Sixth IEEE International High-Level Design Validation and Test Workshop\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HLDVT.2001.972804\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Sixth IEEE International High-Level Design Validation and Test Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HLDVT.2001.972804","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Estimating the relative single stuck-at fault coverage of test sets for a combinational logic block from its functional description
When the gate-level description of a logic block is unknown, it may become necessary to estimate the gate-level stuck-at fault coverage of a test set for the block by using a fault coverage metric that does not require simulation of gate-level faults. We propose such a metric based on stuck-at faults on primary inputs of the block We show that the proposed metric is accurate in predicting the relative gate-level stuck-at fault coverage of different test sets.