Experience with term level modeling and verification of the M*CORE/sup TM/ microprocessor core

Sixth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2001-12-07 DOI:10.1109/HLDVT.2001.972816

Shuvendu K. Lahiri, C. Pixley, Ken Albin

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引用次数: 34

Abstract

The paper describes the use of term-level modeling and verification of an industrial microprocessor, M*CORE/sup TM/ which is a limited dual-issue, super-scalar processor with instruction prefetching mechanism, deep pipeline, multicycle functional units, speculation and interlocks. Term-level modeling uses terms, uninterpreted functions and predicates to abstract the data path complexity of the microprocessor. The verification of the control path is carried out almost mechanically with the aid of CMU-EVC, an extremely efficient decision procedure based on the Logic of Positive Equality with Uninterpreted Functions (PEUF). The verification effort resulted in detection of a couple of non-trivial bugs in the microarchitecture in design exploration phase of the design. The paper demonstrates the effectiveness of CMU-EVC for automated verification of real-life microprocessor designs and also points out some of the challenges and the future work that need to be addressed in term-level modeling and verification of microprocessors using CMU-EVC.

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具有M*CORE/sup TM/微处理器核心的术语级建模和验证经验

本文描述了一种工业微处理器M*CORE/sup TM/的术语级建模和验证方法。M*CORE/sup TM/是一种具有指令预取机制、深管道、多循环功能单元、推测和联锁的有限双问题、超大标量处理器。术语级建模使用术语、未解释函数和谓词来抽象微处理器的数据路径复杂性。控制路径的验证几乎是机械地借助CMU-EVC进行的，CMU-EVC是一种基于未解释函数正相等逻辑(PEUF)的极其有效的决策过程。在设计的设计探索阶段，验证工作导致在微架构中检测到一些重要的错误。本文论证了CMU-EVC在实际微处理器设计自动验证方面的有效性，并指出了在使用CMU-EVC对微处理器进行术语级建模和验证时需要解决的一些挑战和未来的工作。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Sixth IEEE International High-Level Design Validation and Test Workshop

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