Reducing bitvector satisfiability problems to scale down design sizes for RTL property checking

Abstract

Formal bitvector theories have proven to be an adequate means of describing digital hardware at a higher level of design abstraction. Digital designs can be characterized by bitvector equations, such that design properties can be verified by determining satisfiability of such equations. Usually, satisfiability is checked in the Boolean domain by transforming systems of bitvector equations into Boolean formulae and afterwards applying bit-level verification techniques, like SAT and BDD procedures. The complexity of these methods often depends on the number of bit-level variables in the Boolean formulae, and thus depends on the sum of the widths of all bitvectors occurring in the equations. This paper presents a technique to reduce a system of equations over bitvectors of certain width into an equivalent system with smaller widths, while preserving satisfiability of the equations in a one-to-one fashion. The proposed reduction technique provides an efficient way to compute satisfying solutions of the original system from satisfying solutions found for the reduced system. We show how this technique can be used to speed up property checking of digital hardware by scaling down design sizes before verification.