{"title":"嵌入式多处理器SoC通信硬件/软件实现的快速时序协同仿真","authors":"S. Yoo, G. Nicolescu, L. Gauthier, A. Jerraya","doi":"10.1109/HLDVT.2001.972811","DOIUrl":null,"url":null,"abstract":"To fast evaluate HW/SW implementation of multiprocessor SoC communication, we present a method to simulate operating systems (OSs) on a simulation host without running instruction set simulators and generic OS simulation models. The method enables fast timed OS simulation including the preemption of task execution. Together with the fast simulation of synthesizable HW code (e.g. in synthesizable C), it will enable fast evaluation of HW/SW implementation of multiprocessor SoC communication.","PeriodicalId":188469,"journal":{"name":"Sixth IEEE International High-Level Design Validation and Test Workshop","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Fast timed cosimulation of HW/SW implementation of embedded multiprocessor SoC communication\",\"authors\":\"S. Yoo, G. Nicolescu, L. Gauthier, A. Jerraya\",\"doi\":\"10.1109/HLDVT.2001.972811\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"To fast evaluate HW/SW implementation of multiprocessor SoC communication, we present a method to simulate operating systems (OSs) on a simulation host without running instruction set simulators and generic OS simulation models. The method enables fast timed OS simulation including the preemption of task execution. Together with the fast simulation of synthesizable HW code (e.g. in synthesizable C), it will enable fast evaluation of HW/SW implementation of multiprocessor SoC communication.\",\"PeriodicalId\":188469,\"journal\":{\"name\":\"Sixth IEEE International High-Level Design Validation and Test Workshop\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-12-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Sixth IEEE International High-Level Design Validation and Test Workshop\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HLDVT.2001.972811\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Sixth IEEE International High-Level Design Validation and Test Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HLDVT.2001.972811","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Fast timed cosimulation of HW/SW implementation of embedded multiprocessor SoC communication
To fast evaluate HW/SW implementation of multiprocessor SoC communication, we present a method to simulate operating systems (OSs) on a simulation host without running instruction set simulators and generic OS simulation models. The method enables fast timed OS simulation including the preemption of task execution. Together with the fast simulation of synthesizable HW code (e.g. in synthesizable C), it will enable fast evaluation of HW/SW implementation of multiprocessor SoC communication.
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