An enhanced cut-points algorithm in formal equivalence verification

Abstract

BDD-based cut-points verification is widely used informal verification. The authors have recently developed a cut-points verification algorithm that is unique in that it avoids generation of false-negatives and allows simplification of the circuits to be compared based on reconvergence of input variables. Here we describe several refinements and enhancements that lead both to drastic speedup as well increase in capacity. These methods are already implemented in Intel's combinational verifier CLEVER and show very promising results on real life examples from the pentium design family.