2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems最新文献_第7页

System-level performance optimization and benchmarking for on-chip graphene interconnects 片上石墨烯互连的系统级性能优化和基准测试

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems Pub Date : 2012-10-01 DOI: 10.1109/EPEPS.2012.6457837

C. Pan, A. Naeemi

引用次数: 7

Thermal characterization of TSV based 3D stacked ICs 基于TSV的3D堆叠ic热特性研究

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems Pub Date : 2012-10-01 DOI: 10.1109/EPEPS.2012.6457910

S. Swarup, S. Tan, Zao Liu

{"title":"Thermal characterization of TSV based 3D stacked ICs","authors":"S. Swarup, S. Tan, Zao Liu","doi":"10.1109/EPEPS.2012.6457910","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457910","url":null,"abstract":"This paper studies the thermal impact and characterization of Through Silicon Vias (TSVs) in stacked three dimensional (3D) integrated circuits (ICs) through finite-element based numerical analysis. Realistic 3D stacked ICs are built using a commercial finite-element based modeling and analysis tool, COMSOL. Thermal profiles along with thermal impact of TSVs are studied for two layer and three layer stacked IC structures under practical power inputs. Experimental results show that there is a significant temperature gradient across the stacked dies for both two layer and three layer structures. The cross-layer temperature is seen to grow rapidly from two layer structures to three layer structures with the same power and TSV densities. As a result, stacking of active layers will not be scalable as the maximum temperature can quickly reach the 105 degree Centigrade limit for CMOS technology. Elevated temperatures can make thermal-sensitive reliability issues a major challenge for 3D stacked ICs. Advanced cooling, low power design, better thermal management and new architecture techniques are hence required to keep the temperature in a safe range for stacking more layers onto the chip.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115168761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Crosstalk through finite ground 通过有限地的串扰

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems Pub Date : 2012-10-01 DOI: 10.1109/EPEPS.2012.6457877

Long Yang, J. Umaretiya

引用次数: 1

An unconditionally stable finite-element timedomain layered domain-decomposition algorithm for simulating 3D high-speed circuits 三维高速电路仿真的无条件稳定有限元时域分层域分解算法

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems Pub Date : 2012-10-01 DOI: 10.1109/EPEPS.2012.6457867

Xiaolei Li, Jianming Jin

引用次数: 2

Minimizing simultaneous switching noise at reduced power with power transmission lines for high-speed signaling 最大限度地减少同时开关噪声在降低功率与电力传输线路的高速信号

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems Pub Date : 2012-10-01 DOI: 10.1109/EPEPS.2012.6457836

Satyanarayana Telikepalli, Madhavan Swaminathan, D. Keezer

引用次数: 2

S-parameter based multimode signaling 基于s参数的多模信令

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems Pub Date : 2012-10-01 DOI: 10.1109/EPEPS.2012.6457832

Zhuo Yan, Chanyoun Won, P. Franzon, K. Aygun, H. Braunisch

引用次数: 5

A partial homomorphic encryption scheme for secure design automation on public clouds 一种用于公共云安全设计自动化的部分同态加密方案

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems Pub Date : 2012-10-01 DOI: 10.1109/EPEPS.2012.6457871

A. Yu, A. Sathanur, V. Jandhyala

引用次数: 5

Chip oriented target impedance for digital power distribution network design 面向芯片的数字配电网目标阻抗设计

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems Pub Date : 2012-10-01 DOI: 10.1109/EPEPS.2012.6457881

M. Tanaka, M. Toyama, H. Nakashima, J. Yamada, M. Haida, I. Ooshima

{"title":"Chip oriented target impedance for digital power distribution network design","authors":"M. Tanaka, M. Toyama, H. Nakashima, J. Yamada, M. Haida, I. Ooshima","doi":"10.1109/EPEPS.2012.6457881","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457881","url":null,"abstract":"With the advancements in semiconductor process technologies in recent years, noise management has become more difficult. Therefore power distribution network (PDN) design has become more important. This paper describes the target impedance build method. The key techniques are to find the impedance border line of normal chip operation and to set the target impedance which does not exceed that border line. The target impedance which is produced by the proposed method is useful in optimizing the design margin and reducing the chip/package/board size. From the experimental result using a 45-nm process Test Element Group (TEG) chip, the package size was reduced by 21.5%, and the chip size was reduced by 16.4% in comparison with the original design which was not designed using the target impedance. Furthermore, normal chip operation was confirmed by the actual measurement. On the other hand, a working design pattern was not able to be found in the target impedance which was produced by the conventional method. The experimental result demonstrates the validation of the proposed method.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125394468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

On analytic model of multiple vias for high-speed printed circuit board and electric band-gap structures 高速印刷电路板多通孔及电带隙结构的解析模型

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems Pub Date : 2012-10-01 DOI: 10.1109/EPEPS.2012.6457904

Lisha Zhang, G. Pan, Zhonghai Guo

引用次数: 0

Simulation and measurement correlation of random rough surface effects in interconnects 互连中随机粗糙表面效应的仿真与测量相关性

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems Pub Date : 2012-10-01 DOI: 10.1109/EPEPS.2012.6457894

R. Ding, H. Braunisch, L. Tsang, Wenmo Chang

{"title":"Simulation and measurement correlation of random rough surface effects in interconnects","authors":"R. Ding, H. Braunisch, L. Tsang, Wenmo Chang","doi":"10.1109/EPEPS.2012.6457894","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457894","url":null,"abstract":"We study the effects of three dimensional (3D) random roughness on wave propagation in a parallel plate metallic waveguide with finite conductivity. The surface roughness is characterized as a random process characterized by root mean square (rms) height, correlation length and power spectral density (PSD) function. The second order small perturbation method (SPM2) is applied to compute the coherent wave enhancement factors of absorption. A microstrip line structure is designed for validation of these enhancement factor results. Rough surface height profiles are measured on the substrate and the PSD is extracted. With the PSD we obtain the enhancement factor for the specific surface roughness. The attenuation constant of the microstrip line with rough surface can be estimated using a field solution for a smooth surface and the enhancement factor. The results for waveguides are also compared with the results obtained for a plane wave incident on a metal surface with 3D roughness. Comparison between the estimated and measured attenuation constant shows that the enhancement factor derived by SPM2 gives a better estimation than the standard Hammerstad and Bekkadal equation. The waveguide model gives more accurate enhancement factors than the plane wave model at frequencies above 20 GHz, especially for rough surfaces with rms heights larger than 2 μm.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"30 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130277787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6