2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems最新文献

Modeling and analysis of SSN in silicon and glass interposers for 3D systems 三维系统中硅和玻璃中间层SSN的建模与分析

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems Pub Date : 2012-10-01 DOI: 10.1109/EPEPS.2012.6457893

Biancun Xie, Madhavan Swaminathan

引用次数: 10

Enhanced eye-height estimation of mismatched lossy transmission lines 非匹配有损传输线眼高估计的增强

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems Pub Date : 2012-10-01 DOI: 10.1109/EPEPS.2012.6457860

Shih-Ya Huang, Yung-Shou Cheng, Bob Liu, R. Wu

引用次数: 2

Graphene-based EMI shielding for vertical noise coupling reduction in 3D mixed-signal system 三维混合信号系统中基于石墨烯的电磁干扰屏蔽降低垂直噪声耦合

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems Pub Date : 2012-10-01 DOI: 10.1109/EPEPS.2012.6457862

Kiyeong Kim, Kyoungchoul Koo, Seulki Hong, Jonghoon J. Kim, Byung-Ho Cho, Joungho Kim

{"title":"Graphene-based EMI shielding for vertical noise coupling reduction in 3D mixed-signal system","authors":"Kiyeong Kim, Kyoungchoul Koo, Seulki Hong, Jonghoon J. Kim, Byung-Ho Cho, Joungho Kim","doi":"10.1109/EPEPS.2012.6457862","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457862","url":null,"abstract":"Vertical noise coupling caused by the near-field coupling between the RF/analog IC and logic IC is a severe problem in 3D mixed-signal systems. To reduce the vertical noise coupling, graphene is an appropriate material due to its inherent characteristics such as very low thickness, high flexibility, high mechanical strength, and EMI absorbing characteristic. Especially, the EMI absorbing characteristic is an important property as the shield to prevent the vertical noise coupling, as it reduces the re-coupling of the reflected EMI by the shield into other ICs. We measure the reduction of the vertical noise coupling by the mono-layer graphene shield in the 3D mixed-signal system composed of a low noise amplifier (LNA), an on-chip switching model DC-DC converter, and the mono-layer graphene in the frequency and time domain. Through the measurement results, we observed that the mono-layer graphene can maximally reduce the vertical noise coupling by -17 dB in the frequency domain. Additionally, the vertically coupled noise is reduced by 25% in the time domain measurement.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116162968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Bandwidth and gain enhancement of antenna in package 封装天线的带宽和增益增强

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems Pub Date : 2012-10-01 DOI: 10.1109/EPEPS.2012.6457863

Z. Tong, A. Fischer, A. Stelzer, L. Maurer

引用次数: 2

An efficient method for transient simulation of high-speed interconnects with nonlinear terminations 具有非线性终端的高速互连暂态仿真的一种有效方法

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems Pub Date : 2012-10-01 DOI: 10.1109/EPEPS.2012.6457856

M. Farhan, E. Gad, M. Nakhla, R. Achar

引用次数: 0

Chip-package co-design for suppressing parallel resonance and power supply noise 抑制并行谐振和电源噪声的芯片封装协同设计

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems Pub Date : 2012-10-01 DOI: 10.1109/EPEPS.2012.6457913

T. Mido, R. Kobayashi, G. Kubo, H. Otsuka, Y. Kobayashi, H. Fujii, T. Sudo

{"title":"Chip-package co-design for suppressing parallel resonance and power supply noise","authors":"T. Mido, R. Kobayashi, G. Kubo, H. Otsuka, Y. Kobayashi, H. Fujii, T. Sudo","doi":"10.1109/EPEPS.2012.6457913","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457913","url":null,"abstract":"Power integrity is a serious issue in the modern CMOS digital systems, because power supply noise excited in core circuits induces logic instability and electromagnetic radiation. Therefore, chip-package co-design is becoming important by taking into consideration the total impedance of power distribution network (PDN) seen from the chip. Especially, parallel resonance peaks in the PDN due to the chip-package interaction induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by adding different RC circuit to the intrinsic on-die RC circuit of chip. Three test chips were assumed to be designed with different on-chip PDN properties. The simulated power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116201039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Millimeter-wave coplanar interconnects and radiators on FR-4 laminates FR-4层压板上的毫米波共面互连和散热器

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems Pub Date : 2012-10-01 DOI: 10.1109/EPEPS.2012.6457912

S. Aroor, R. Pierce, R. Henderson, A. Blanchard

引用次数: 3

Eye diagram parameter extraction of nano scale VLSI interconnects 纳米级VLSI互连眼图参数提取

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems Pub Date : 2012-10-01 DOI: 10.1109/EPEPS.2012.6457908

M. Mehri, R. Sarvari, A. Seydolhosseini

引用次数: 0

Fast assessment of the impact of surrounding wiring on the transmission properties of high-speed interconnect channels 高速互连通道周围布线对传输特性影响的快速评估

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems Pub Date : 2012-10-01 DOI: 10.1109/EPEPS.2012.6457845

Joon Hyung Chung, A. Cangellaris

{"title":"Fast assessment of the impact of surrounding wiring on the transmission properties of high-speed interconnect channels","authors":"Joon Hyung Chung, A. Cangellaris","doi":"10.1109/EPEPS.2012.6457845","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457845","url":null,"abstract":"A methodology is proposed for the fast assessment of the impact of electromagnetic loading by surrounding wiring on the signal transmission properties of a high-speed interconnect channel. The proposed methodology is aimed at alleviating the computational complexity of the electromagnetic modeling of the channel including the details of the wiring in its surrounding that, more often than not and especially in the early stages of design, are not well defined and thus are best accounted for through a Monte Carlo analysis. Instead, use of a stochastic macromodel for the channel is proposed that incorporates the electromagnetic attributes of the surrounding wiring through a statistical description of its loading on the interconnects of the channel. The proposed method makes use of parametric rational interpolation to develop a frequency-dependent macromodel that is valid over the multi-dimensional space that describes the uncertainty of the neighboring layout topography. Making use of stochastic collocation, the channel macromodel lends itself to fast quantitative analysis of the channel transmission properties and signal degradation in both frequency and time domain. A simple channel example, which allows us to assess the accuracy of the proposed method, is used to demonstrate the key attributes of the proposed method and comment on its usefulness as a computer-aided tool for noise-aware wiring layout planning.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124623201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Modeling and measurement of supply noise induced jitter in a 12.8Gbps single-ended memory interface 12.8Gbps单端存储接口中电源噪声诱发抖动的建模与测量

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems Pub Date : 2012-10-01 DOI: 10.1109/EPEPS.2012.6457839

H. Lan, Minghui Han, R. Schmitt

引用次数: 10