12.8Gbps单端存储接口中电源噪声诱发抖动的建模与测量

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems Pub Date : 2012-10-01 DOI:10.1109/EPEPS.2012.6457839

H. Lan, Minghui Han, R. Schmitt

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引用次数: 10

摘要

分析电源噪声特性并预测其抖动影响对于设计12.8Gbps单端存储接口以实现优于5mW/Gbps的能效至关重要。时钟电路的抖动性能以抖动灵敏度为特征。将噪声谱与灵敏度曲线相结合，导出了电源噪声诱发抖动(PSIJ)。最终的PSIJ预测与片上测量结果非常吻合。

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Modeling and measurement of supply noise induced jitter in a 12.8Gbps single-ended memory interface

Analyzing power supply noise characteristics and predicting its jitter impact is critical in designing the 12.8Gbps single-ended memory interface achieving better than 5mW/Gbps energy efficiency. The clocking circuit jitter performance is characterized by jitter sensitivity. The power supply noise induced jitter (PSIJ) is derived by combining the noise spectrum and sensitivity profile. The final PSIJ prediction matches closely with the on-chip measurement result.

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来源期刊

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems

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