Chip-package co-design for suppressing parallel resonance and power supply noise

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems Pub Date : 2012-10-01 DOI:10.1109/EPEPS.2012.6457913

T. Mido, R. Kobayashi, G. Kubo, H. Otsuka, Y. Kobayashi, H. Fujii, T. Sudo

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引用次数: 2

Abstract

Power integrity is a serious issue in the modern CMOS digital systems, because power supply noise excited in core circuits induces logic instability and electromagnetic radiation. Therefore, chip-package co-design is becoming important by taking into consideration the total impedance of power distribution network (PDN) seen from the chip. Especially, parallel resonance peaks in the PDN due to the chip-package interaction induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by adding different RC circuit to the intrinsic on-die RC circuit of chip. Three test chips were assumed to be designed with different on-chip PDN properties. The simulated power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip.

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抑制并行谐振和电源噪声的芯片封装协同设计

电源完整性是现代CMOS数字系统中的一个重要问题，因为电源噪声在核心电路中会引起逻辑不稳定和电磁辐射。因此，从芯片上考虑配电网络(PDN)的总阻抗，芯片封装协同设计变得越来越重要。特别是PDN中由于芯片与封装的相互作用而产生的并联共振峰，引起了不必要的电源波动，导致了信号完整性的降低和电磁干扰(EMI)。本文通过在芯片的片内RC电路中加入不同的RC电路，研究了PDN总阻抗的临界阻尼条件对电源噪声的影响。假设三个测试芯片具有不同的片上PDN特性。三种测试芯片的模拟电源噪声均表现出典型的振荡区和阻尼区特征，抗共振峰处的临界阻尼条件能够有效抑制芯片上的电源噪声。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems

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