Chip oriented target impedance for digital power distribution network design

Abstract

With the advancements in semiconductor process technologies in recent years, noise management has become more difficult. Therefore power distribution network (PDN) design has become more important. This paper describes the target impedance build method. The key techniques are to find the impedance border line of normal chip operation and to set the target impedance which does not exceed that border line. The target impedance which is produced by the proposed method is useful in optimizing the design margin and reducing the chip/package/board size. From the experimental result using a 45-nm process Test Element Group (TEG) chip, the package size was reduced by 21.5%, and the chip size was reduced by 16.4% in comparison with the original design which was not designed using the target impedance. Furthermore, normal chip operation was confirmed by the actual measurement. On the other hand, a working design pattern was not able to be found in the target impedance which was produced by the conventional method. The experimental result demonstrates the validation of the proposed method.