2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems最新文献

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Frequency domain analysis of jitter amplification in clock channels 时钟通道中抖动放大的频域分析
F. Rao, S. Hindi
{"title":"Frequency domain analysis of jitter amplification in clock channels","authors":"F. Rao, S. Hindi","doi":"10.1109/EPEPS.2012.6457841","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457841","url":null,"abstract":"Clock channel jitter amplification factor in terms of transfer function or S-parameters is derived. Amplification is shown to arise from smaller attenuation in jitter lower sideband than in the fundamental. Amplification scaling with loss is obtained analytically.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123199676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
On aperture coupling based compact system of lens enhanced phased array 基于孔径耦合的透镜增强相控阵紧凑系统研究
Lisha Zhang, A. Abbaspour-Tamijani, G. Pan, H. Pan
{"title":"On aperture coupling based compact system of lens enhanced phased array","authors":"Lisha Zhang, A. Abbaspour-Tamijani, G. Pan, H. Pan","doi":"10.1109/EPEPS.2012.6457899","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457899","url":null,"abstract":"We present design and implementation of the aperture coupling based compact system of lens enhanced phased array (LEPA) for 60 GHz band high-speed internet, data and voice channels. The LEPA is a high-directivity steerable integrated system without putting penalties on the chip size and DC power consumption. The core of a LEPA is composed of the antenna-filter-antenna (AFA) structures consisting of two layers of 15 mil-thick low-loss microwave laminates and three 18um-thick copper layers. An incident wave with proper polarization is received by the top slot in the input side, passes through a half-wave stripline resonator, and then reradiates from the bottom slot on the output side with orthogonal polarization. Vias surrounding AFA elements guarantee that no parallel plate modes are excited between the two grounds, while any surface wave modes formed on the reactive surface of the array may still contribute to the occurrence of blind scan angles and need to be suppressed.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128123334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A mixed-domain behavioral model's extraction for digital I/O buffers 数字I/O缓冲区混合域行为模型的提取
W. Dghais, T. Cunha, J. Pedro
{"title":"A mixed-domain behavioral model's extraction for digital I/O buffers","authors":"W. Dghais, T. Cunha, J. Pedro","doi":"10.1109/EPEPS.2012.6457882","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457882","url":null,"abstract":"The paper presents a novel extraction procedure based on the frequency domain formulation of the current-charge (I-Q) behavioral model for digital I/O buffers/drivers output admittance followed by a time domain extraction of the predriver's nonlinear dynamic functions. The large signal model's functions of the drivers' output admittance are derived from the bias-dependent scattering, or S-parameters, measurements. This easy and fast extraction method allows the accurate generation of the data-based model from automated and straightforward measurements. The extracted model's functions are implemented as lookup tables (LUTs) and the behavioral model is validated in typical SI scenario.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134560882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Current distribution and internal impedance of interconnect 互连电流分布和内部阻抗
Hongsheng Xu, Jiming Song, T. Kamgaing
{"title":"Current distribution and internal impedance of interconnect","authors":"Hongsheng Xu, Jiming Song, T. Kamgaing","doi":"10.1109/EPEPS.2012.6457903","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457903","url":null,"abstract":"A novel volume integral equation for the current distribution over interconnects with arbitrary cross-sectional geometry is presented based on the free space Green's function without approximation. For very low frequency, it can be reduced to the widely-used quasi-static approximation. The quasi-static volume integral equation is not accurate enough for the calculation of current distribution. A comparison is made with the different methods known in literature to calculate the per unit length internal impedance. Detailed discussion is given for the different current distributions and the definitions with their effects to the internal impedance, either for a high frequency range or a low frequency range.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131017168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Simultaneous switching noise analysis of reference voltage rails for pseudo differential interfaces 伪差分接口参考电压轨同步开关噪声分析
Sung Joo Park, J. Choi, Madhavan Swaminathan
{"title":"Simultaneous switching noise analysis of reference voltage rails for pseudo differential interfaces","authors":"Sung Joo Park, J. Choi, Madhavan Swaminathan","doi":"10.1109/EPEPS.2012.6457840","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457840","url":null,"abstract":"Single-ended (SE) signaling is preferable than differential signaling in high-speed memory interface designs, mainly because of less power and pin-count requirements. However, SE signaling is vulnerable to simultaneous switching noise (SSN) which is a major performance limiter. SSN is a function of the inductance of power and ground planes, which are the return paths for data signal lines. In recent literature, an assertion was posed that the impact of plane bounce on the SE signaling is not significant due to the compensation of noise by the voltage reference rail. In this paper, we set forth a counter-argument by presenting the noise analyses focusing on the impact of various voltage reference designs. In addition, we also show the decoupling method for a system using multiple voltages.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114648940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Novel crosstalk modeling for multiple through-silicon-vias (TSV) on 3-D IC: Experimental validation and application to Faraday cage design 三维集成电路上多通硅孔(TSV)串扰建模:实验验证及其在法拉第笼设计中的应用
Yu-Jen Chang, Hao-Hsiang Chuang, Yi-Chang Lu, Y. Chiou, Tzong-Lin Wu, P. Chen, Shih-Hsien Wu, T. Kuo, C. Zhan, W. Lo
{"title":"Novel crosstalk modeling for multiple through-silicon-vias (TSV) on 3-D IC: Experimental validation and application to Faraday cage design","authors":"Yu-Jen Chang, Hao-Hsiang Chuang, Yi-Chang Lu, Y. Chiou, Tzong-Lin Wu, P. Chen, Shih-Hsien Wu, T. Kuo, C. Zhan, W. Lo","doi":"10.1109/EPEPS.2012.6457884","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457884","url":null,"abstract":"An equivalent circuit model to characterize the crosstalk strength in multiple TSVs is newly proposed. In this model, all the values of lumped elements in the model are given in closed-form formulas. Therefore, the computation effort for constructing the model of multiple TSVs is much lower than other previous works. The accuracy is verified by the measurement for a nine stacked silicon chips and the full-wave simulation results. The proposed model is then utilized to the design for crosstalk mitigation. With the advantages of smaller occupied area (lower cost), a rhombus-grounded Faraday cage design is recommended with lower cost and similar performance compared to conventional Faraday cage concept.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126067778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A compact on-interposer passive equalizer for chip-to-chip high-speed data transmission 用于芯片到芯片高速数据传输的紧凑型介入器无源均衡器
Heegon Kim, Jonghyun Cho, Joohee Kim, Kiyeong Kim, Sumin Choi, Joungho Kim, J. Pak
{"title":"A compact on-interposer passive equalizer for chip-to-chip high-speed data transmission","authors":"Heegon Kim, Jonghyun Cho, Joohee Kim, Kiyeong Kim, Sumin Choi, Joungho Kim, J. Pak","doi":"10.1109/EPEPS.2012.6457851","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457851","url":null,"abstract":"In this paper, a new compact on-interposer passive equalizer was proposed for chip-to-chip high-speed data transmission on the silicon-based on-interposer channel. The proposed equalizer uses the parasitic resistance and inductance of the coil-shaped on-interposer shunt metal line structure to produce the high-pass filter for loss compensation. This results in wide-band channel equalization and low power-consumption. Moreover, the compact coil-shaped structure of the proposed equalizer allows for wide I/O and high adjustability. The remarkable performance of the proposed compact on-interposer passive equalizer is successfully demonstrated by a frequency-and time-domain simulation of up to 10 Gbps.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125140321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
System-level performance optimization and benchmarking for on-chip graphene interconnects 片上石墨烯互连的系统级性能优化和基准测试
C. Pan, A. Naeemi
{"title":"System-level performance optimization and benchmarking for on-chip graphene interconnects","authors":"C. Pan, A. Naeemi","doi":"10.1109/EPEPS.2012.6457837","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457837","url":null,"abstract":"In this paper, graphene interconnects are analyzed and benchmarked against conventional copper wires, indicating the advantage of using graphene at a short wire length or being driven by a device with a large output resistance. For the first time, a system-level optimization of graphene interconnects is performed for both single- and multi-core chips. It is found that under the same power density and die size area, an optimized multi-core processor using graphene as short interconnects can provide up to 25% and 55% improvements in throughput and energy × execution time per instruction, respectively.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125944143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Thermal characterization of TSV based 3D stacked ICs 基于TSV的3D堆叠ic热特性研究
S. Swarup, S. Tan, Zao Liu
{"title":"Thermal characterization of TSV based 3D stacked ICs","authors":"S. Swarup, S. Tan, Zao Liu","doi":"10.1109/EPEPS.2012.6457910","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457910","url":null,"abstract":"This paper studies the thermal impact and characterization of Through Silicon Vias (TSVs) in stacked three dimensional (3D) integrated circuits (ICs) through finite-element based numerical analysis. Realistic 3D stacked ICs are built using a commercial finite-element based modeling and analysis tool, COMSOL. Thermal profiles along with thermal impact of TSVs are studied for two layer and three layer stacked IC structures under practical power inputs. Experimental results show that there is a significant temperature gradient across the stacked dies for both two layer and three layer structures. The cross-layer temperature is seen to grow rapidly from two layer structures to three layer structures with the same power and TSV densities. As a result, stacking of active layers will not be scalable as the maximum temperature can quickly reach the 105 degree Centigrade limit for CMOS technology. Elevated temperatures can make thermal-sensitive reliability issues a major challenge for 3D stacked ICs. Advanced cooling, low power design, better thermal management and new architecture techniques are hence required to keep the temperature in a safe range for stacking more layers onto the chip.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115168761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Electrical interconnect design for testing of high-speed IC transceivers 高速集成电路收发器测试的电气互连设计
R. Rímolo-Donadío, C. Baks, B. Lee, J. H. Song, X. Gu, Y. Kwark, D. Kuchta, A. Rylyakov, C. Schow
{"title":"Electrical interconnect design for testing of high-speed IC transceivers","authors":"R. Rímolo-Donadío, C. Baks, B. Lee, J. H. Song, X. Gu, Y. Kwark, D. Kuchta, A. Rylyakov, C. Schow","doi":"10.1109/EPEPS.2012.6457842","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457842","url":null,"abstract":"This paper discusses the requirements and challenges associated with the design of electrical interconnects to support the test and evaluation of high-speed transceivers working up to 40 Gb/s. It will be shown that relatively low cost technologies such as FR-4 boards, push-on connectors, and wire bonding can effectively achieve this goal. A specific platform and its application for testing of a 40-Gb/s VCSEL-based optoelectronic link are presented.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125220201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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