Electrical interconnect design for testing of high-speed IC transceivers

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems Pub Date : 2012-10-01 DOI:10.1109/EPEPS.2012.6457842

R. Rímolo-Donadío, C. Baks, B. Lee, J. H. Song, X. Gu, Y. Kwark, D. Kuchta, A. Rylyakov, C. Schow

引用次数: 1

Abstract

This paper discusses the requirements and challenges associated with the design of electrical interconnects to support the test and evaluation of high-speed transceivers working up to 40 Gb/s. It will be shown that relatively low cost technologies such as FR-4 boards, push-on connectors, and wire bonding can effectively achieve this goal. A specific platform and its application for testing of a 40-Gb/s VCSEL-based optoelectronic link are presented.

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高速集成电路收发器测试的电气互连设计

本文讨论了与电气互连设计相关的要求和挑战，以支持高达40 Gb/s的高速收发器的测试和评估。将表明，相对低成本的技术，如FR-4板，推入式连接器和线键合可以有效地实现这一目标。介绍了40 gb /s vcsel光电链路测试的具体平台及其应用。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems

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