System-level performance optimization and benchmarking for on-chip graphene interconnects

Abstract

In this paper, graphene interconnects are analyzed and benchmarked against conventional copper wires, indicating the advantage of using graphene at a short wire length or being driven by a device with a large output resistance. For the first time, a system-level optimization of graphene interconnects is performed for both single- and multi-core chips. It is found that under the same power density and die size area, an optimized multi-core processor using graphene as short interconnects can provide up to 25% and 55% improvements in throughput and energy × execution time per instruction, respectively.