Proceedings of the Great Lakes Symposium on VLSI 2022最新文献_第5页

Side-Channel Analysis of the Random Number Generator in STM32 MCUs STM32单片机中随机数发生器的侧信道分析

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530324

Kalle Ngo, E. Dubrova

引用次数: 6

Benchmark Comparisons of Spike-based Reconfigurable Neuroprocessor Architectures for Control Applications 控制应用中基于峰值的可重构神经处理器架构的基准比较

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530381

Adam Z. Foshie, Charles Rizzo, Hritom Das, Chaohui Zheng, J. Plank, G. Rose

引用次数: 7

An Effective Test Method for Block RAMs in Heterogeneous FPGAs Based on a Novel Partial Bitstream Relocation Technique 基于部分位流重定位技术的异构fpga块ram测试方法

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530317

Wei-Xi Xiong, Yanze Li, Changpeng Sun, Huanlin Luo, Jiafeng Liu, Jian Wang, Jinmei Lai, G. Qu

{"title":"An Effective Test Method for Block RAMs in Heterogeneous FPGAs Based on a Novel Partial Bitstream Relocation Technique","authors":"Wei-Xi Xiong, Yanze Li, Changpeng Sun, Huanlin Luo, Jiafeng Liu, Jian Wang, Jinmei Lai, G. Qu","doi":"10.1145/3526241.3530317","DOIUrl":"https://doi.org/10.1145/3526241.3530317","url":null,"abstract":"Block RAMs (BRAMs) play an important role in modern heterogenous FPGAs, hence how to test them comprehensively and effectively becomes a major concern. On-chip Partial Bitstream Relocation (PBR) technique based on FPGA Dynamic Partial Reconfiguration (DPR) can decrease the time spent on configuring modules in FPGA while reducing the memory resources overhead for storing partial bitstreams of the reconfigurable modules. The previous PBR technique is difficult to be combined with BRAM test directly, because they are somehow tedious, unsuitable for large-scale design or limited to specific devices. Besides, the problem exists for BRAM testing is that fault model is still incomplete and testing algorithms need to be improved to achieve higher fault coverage. An Effective BRAM test method based on a novel PBR technique is proposed in this paper. Our test method establishes a complete fault model for BRAM and improves the testing algorithms for faults in BRAM ECC circuits and intra-word coupling faults in SRAM cells. On-board experiments are carried out with Xilinx xc7vx690t device, and 14 BRAM configurations are used to fully test BRAMs. In conjunction with the proposed PBR technique, the number of configurations can be reduced to 10, which leads to a 35.7% time saving.","PeriodicalId":188228,"journal":{"name":"Proceedings of the Great Lakes Symposium on VLSI 2022","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130827623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Session details: Session 3B: VLSI for Machine Learning and Artifical Intelligence 1 会议详情:3B: VLSI用于机器学习和人工智能

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3542687

J. Hu

引用次数: 0

Design and Evaluation of In-Exact Compressor based Approximate Multipliers 基于精确压缩器的近似乘法器设计与评价

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530320

C. PrashanthH., R. SoujanyaS., Bindu G. Gowda, M. Rao

{"title":"Design and Evaluation of In-Exact Compressor based Approximate Multipliers","authors":"C. PrashanthH., R. SoujanyaS., Bindu G. Gowda, M. Rao","doi":"10.1145/3526241.3530320","DOIUrl":"https://doi.org/10.1145/3526241.3530320","url":null,"abstract":"VLSI implementation of arithmetic functions are of high demand considering the rise in hardware realization of image and digital signal processing modules for various autonomous applications. The hardware implementation offers faster results and desirable outcome, but expecting the same design metrics in the form of power, footprint and delay on a tiny decision-making edge devices with limited resources needs design improvisation. Approximate computing promises to support the required hardware metrics in error resilient applications where the inexact output is not deviated much from the expected one, and decision made remains unchanged. Multiplier design blocks are heavily used in the multimedia functional chip, and introducing approximation in these blocks effectively benefits design metrics and chip cost of the developed system-on-chip(SoC). The proposed work attempts to design and use various sizes of approximate AND-OR re-coded compressors in the multiple reduction stages, along with various fast adders in the final addition stage of multiplier design. Further, design metrics and resources utilized for different multiplier designs were characterized in ASIC and FPGA synthesis flows respectively, along with their error statistics. Designed approximate multipliers were employed in Gaussian smoothing application to evaluate the quality-hardware resource trade-off of approximation","PeriodicalId":188228,"journal":{"name":"Proceedings of the Great Lakes Symposium on VLSI 2022","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114343768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

MI2D: Accelerating Matrix Inversion with 2-Dimensional Tile Manipulations MI2D:用二维贴图操作加速矩阵反转

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530314

Lingfeng Chen, Tian Xia, Wenzhe Zhao, Pengju Ren

引用次数: 0

Advanced Environment Modeling and Interaction in an Open Source RISC-V Virtual Prototype 开源RISC-V虚拟样机中的高级环境建模与交互

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530374

Pascal Pieper, V. Herdt, R. Drechsler

{"title":"Advanced Environment Modeling and Interaction in an Open Source RISC-V Virtual Prototype","authors":"Pascal Pieper, V. Herdt, R. Drechsler","doi":"10.1145/3526241.3530374","DOIUrl":"https://doi.org/10.1145/3526241.3530374","url":null,"abstract":"RISC-V is a modern Instruction Set Architecture (ISA) that by its open nature in combination with a clean and modular design has enormous potential to become a game changer in the Internet of Things (IoT) era. Recently, SystemC-based Virtual Prototypes (VPs) have been introduced into the RISC-V ecosystem to lay the foundation for advanced industry-proven system-level use-cases. However, a VP-driven environment modeling and interaction has been mostly neglected in the RISC-V context. In this paper we propose such an extension to broaden the application domain for virtual prototyping in the RISC-V context. As foundation, we build upon the open source RISC-V VP available at GitHub. For visualization purposes of the environment we designed a Graphical User Interface (GUI) and designed appropriate libraries to offer hardware communication interfaces such as GPIO and SPI from the VP to an interactive environment model. Our approach is designed to be integrated with SystemC-based VPs that leverage a Transaction Level Modeling (TLM) communication system to prefer a speed optimized simulation. To show the practicability of an environment model, we provide a set of building blocks such as buttons, LEDs and an OLED display and configure them in two demonstration environments. Our evaluation with three different case-studies demonstrates the applicability of our approach in building virtual environments effectively and correctly in matching the real physical systems. To advance the RISC-V community and stimulate further research we provide our extended VP platform with the environment configuration and visualization toolbox as well as both case-studies as open source on GitHub as well.","PeriodicalId":188228,"journal":{"name":"Proceedings of the Great Lakes Symposium on VLSI 2022","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116611085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Thermal and Power-Aware Run-time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays 集成流电池阵列的3D mpsoc热和功耗感知运行时性能管理

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530309

Halima Najibi, A. Levisse, G. Ansaloni, Marina Zapater, David Atienza Alonso

{"title":"Thermal and Power-Aware Run-time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays","authors":"Halima Najibi, A. Levisse, G. Ansaloni, Marina Zapater, David Atienza Alonso","doi":"10.1145/3526241.3530309","DOIUrl":"https://doi.org/10.1145/3526241.3530309","url":null,"abstract":"Flow Cell Arrays (FCA) technology employs microchannels filled with an electrolytic fluid to concurrently provide cooling and power generation to integrated circuits (ICs). This solution is particularly appealing for Three-Dimensional Multi-Processor Systems-on-Chip (3D MPSoCs) realized in deeply scaled technologies, as their extreme power densities result in significant thermal and voltage supply challenges. FCAs provide them with extra power to boost performance. However, the dual effects of FCAs (cooling and power supply) have conflicting trends leading to a complex interplay between temperature, voltage stability, and performance. In this paper, we explore this trade-off by introducing a novel methodology that controls the operating frequency of computing components and the electrolytic coolant flow rate at run-time. Our strategy enables tangible performance gains while abiding by timing, voltage drop, and temperature constraints. We showcase its benefits by targeting a 4-layer 3D MPSoC, achieving up to 24% increase in the operating frequencies and resulting in application speedups of up to 17%, while reducing the costs related to FCA liquid pumping energy.","PeriodicalId":188228,"journal":{"name":"Proceedings of the Great Lakes Symposium on VLSI 2022","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125890841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance 利用电流源模型和有效电容利用机器学习进行门级定时估计

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530343

Dimitrios Garyfallou, Anastasis Vagenas, Charalampos Antoniadis, Y. Massoud, G. Stamoulis

{"title":"Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance","authors":"Dimitrios Garyfallou, Anastasis Vagenas, Charalampos Antoniadis, Y. Massoud, G. Stamoulis","doi":"10.1145/3526241.3530343","DOIUrl":"https://doi.org/10.1145/3526241.3530343","url":null,"abstract":"With process technology scaling, accurate gate-level timing analysis becomes even more challenging. Highly resistive on-chip interconnects have an ever-increasing impact on timing, signals no longer resemble smooth saturated ramps, while gate-interconnect interdependencies are stronger. Moreover, efficiency is a serious concern since repeatedly invoking a signoff tool during incremental optimization of modern VLSI circuits has become a major bottleneck. In this paper, we introduce a novel machine learning approach for timing estimation of gate-level stages using current source models and the concept of multiple slew and effective capacitance values. First, we exploit a fast iterative algorithm for initial stage timing estimation and feature extraction, and then we employ four artificial neural networks to correlate the initial delay and slew estimates for both the driver and interconnect with golden SPICE results. Contrary to prior works, our method uses fewer and more accurate features to represent the stage, leading to more efficient models. Experimental evaluation on driver-interconnect stages implemented in 7 nm FinFET technology indicates that our method leads to 0.99% (0.90 ps) and 2.54% (2.59 ps) mean error against SPICE for stage delay and slew, respectively. Furthermore, it has a small memory footprint (1.27 MB) and performs 35× faster than a commercial signoff tool. Thus, it may be integrated into timing-driven optimization steps to provide signoff accuracy and expedite timing closure.","PeriodicalId":188228,"journal":{"name":"Proceedings of the Great Lakes Symposium on VLSI 2022","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123677320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

MnM: A Fast and Efficient Min/Max Searching in MRAM MRAM中一种快速有效的最小/最大搜索方法

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530349

Amitesh Sridharan, Fan Zhang, Deliang Fan

引用次数: 1