Proceedings of the Great Lakes Symposium on VLSI 2022最新文献_第4页

Flexible and Personalized Learning for Wearable Health Applications using HyperDimensional Computing 使用超维计算的可穿戴健康应用的灵活和个性化学习

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530373

Sina Shahhosseini, Yang Ni, Emad Kasaeyan Naeini, M. Imani, A. Rahmani, N. Dutt

引用次数: 1

Adapt-Flow: A Flexible DNN Accelerator Architecture for Heterogeneous Dataflow Implementation adaptive - flow:一种灵活的DNN加速器架构，用于异构数据流的实现

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530311

Jiaqi Yang, Hao Zheng, A. Louri

{"title":"Adapt-Flow: A Flexible DNN Accelerator Architecture for Heterogeneous Dataflow Implementation","authors":"Jiaqi Yang, Hao Zheng, A. Louri","doi":"10.1145/3526241.3530311","DOIUrl":"https://doi.org/10.1145/3526241.3530311","url":null,"abstract":"Deep neural networks (DNNs) have been widely applied to various application domains. DNN computation is memory and compute-intensive requiring excessive memory access and a large number of computations. To efficiently implement these applications, several data reuse and parallelism exploitation strategies, called dataflows, have been proposed. Studies have shown that many DNN applications benefit from a heterogeneous dataflow strategy where the dataflow type changes from layer to layer. Unfortunately, very few existing DNN architectures can simultaneously accommodate multiple dataflows due to their limited hardware flexibility. In this paper, we propose a flexible DNN accelerator architecture, called Adapt-Flow, which has the capability of supporting multiple dataflow selections for each DNN layer at runtime. Specifically, the proposed Adapt-Flow architecture consists of (1) a flexible interconnect, (2) a dataflow selection algorithm, and (3) a dataflow mapping technique. The flexible interconnect provides dynamic support for various traffic patterns required by different dataflows. The proposed dataflow selection algorithm selects the optimal dataflow strategy for a given DNN layer with the aim of much improved performance. And the dataflow mapping technique efficiently maps the dataflow amenable to the flexible interconnect. Simulation studies show that the proposed Adapt-Flow architecture reduces execution time by 46%, 78%, 26%, and energy consumption by 45%, 80%, 25% as compared to NVDLA, ShiDianNao, and Eyeriss respectively.","PeriodicalId":188228,"journal":{"name":"Proceedings of the Great Lakes Symposium on VLSI 2022","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129294328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Enhancing Information Security Courses With a Remotely Accessible Side-Channel Analysis Setup 通过远程访问的侧信道分析设置加强信息安全课程

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530347

Abubakr Abdulgadir, J. Kaps, A. Salman

引用次数: 1

ENTANGLE: An Enhanced Logic-locking Technique for Thwarting SAT and Structural Attacks 缠结:一种增强的逻辑锁定技术，用于挫败SAT和结构攻击

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530371

A. Darjani, N. Kavand, Shubham Rai, M. Wijtvliet, Akash Kumar

引用次数: 5

MOCCA: A Process Variation Tolerant Systolic DNN Accelerator using CNFETs in Monolithic 3D MOCCA:在单片3D中使用cnfet的过程变化容忍收缩DNN加速器

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530380

Samuel J. Engers, Cheng Chu, Dawen Xu, Ying Wang, Fan Chen

引用次数: 1

A Memristor-based Secure Scan Design against the Scan-based Side-Channel Attacks 针对扫描侧信道攻击的忆阻器安全扫描设计

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530345

Mengqiang Lu, Aijiao Cui, Yan Shao, G. Qu

引用次数: 0

iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations iMAD: AdderNet的内存加速器，具有高效的8位加减运算

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530313

Shien Zhu, Shiqing Li, Weichen Liu

{"title":"iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations","authors":"Shien Zhu, Shiqing Li, Weichen Liu","doi":"10.1145/3526241.3530313","DOIUrl":"https://doi.org/10.1145/3526241.3530313","url":null,"abstract":"Adder Neural Network (AdderNet) is a new type of Convolutional Neural Networks (CNNs) that replaces the computational-intensive multiplications in convolution layers with lightweight additions and subtractions. As a result, AdderNet preserves high accuracy with adder convolution kernels and achieves high speed and power efficiency. In-Memory Computing (IMC) is known as the next-generation artificial-intelligence computing paradigm that has been widely adopted for accelerating binary and ternary CNNs. As AdderNet has much higher accuracy than binary and ternary CNNs, accelerating AdderNet using IMC can obtain both performance and accuracy benefits. However, existing IMC devices have no dedicated subtraction function, and adding subtraction logic may bring larger area, higher power, and degraded addition performance. In this paper, we propose iMAD as an in-memory accelerator for AdderNet with efficient addition and subtraction operations. First, we propose an efficient in-memory subtraction operator at the circuit level and co-optimize the addition performance to reduce the latency and power. Second, we propose an accelerator architecture for AdderNet with high parallelism based on the optimized operators. Third, we propose an IMC-friendly computation pipeline for AdderNet convolution at the algorithm level to further boost the performance. Evaluation results show that our accelerator iMAD achieves 3.25X speedup and 3.55X energy efficiency compared with a state-of-the-art in-memory accelerator.","PeriodicalId":188228,"journal":{"name":"Proceedings of the Great Lakes Symposium on VLSI 2022","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122032882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Efficient Method for Timing-based Information Flow Verification in Hardware Designs 硬件设计中基于时序的信息流验证方法

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530363

Khitam M. Alatoun, R. Vemuri

引用次数: 0

A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology 一种用于纳米级CMOS技术的高鲁棒、低延迟和dnu恢复锁存器设计

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530321

Aibin Yan, Zhen Zhou, Shaojie Wei, Jie Cui, Yong Zhou, Tianming Ni, P. Girard, X. Wen

引用次数: 1

Session details: Session 6A: Special Session -1: Machine Learning and Hardware Attacks 会议详情:会议6A:特别会议-1:机器学习和硬件攻击

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3542692

Qiaoyan Yu

引用次数: 0