Efficient Method for Timing-based Information Flow Verification in Hardware Designs

Timing side channels are a serious threat to the security of hardware designs. By analyzing the execution times of a design, the attacker can expose the secret information. This paper proposes an approach to verify and monitor timing-based information flow properties. In addition, the method can highlight the path that is vulnerable to leakage, making it easier to trace the leaking channel. The method can be used during formal verification, dynamic verification during simulation, post-fabrication validation, and run-time monitoring if one is necessary. The method reduces the overhead of the security model, which helps speed up the verification process and create an efficient run-time hardware monitor. Various timing-based information flow properties from five different hardware designs were verified. The results show that our approach can accurately detect hardware timing channels with lower overhead.