Proceedings of the Great Lakes Symposium on VLSI 2022最新文献

Loading Effect Free MOS-only Voltage Reference Ladder for ADC in RRAM-crossbar Array 随机存取存储器-横条阵列中ADC的无mos电压参考梯

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530354

Varun Bhatnagar, Gopal R. Raut, S. Vishvakarma

{"title":"Loading Effect Free MOS-only Voltage Reference Ladder for ADC in RRAM-crossbar Array","authors":"Varun Bhatnagar, Gopal R. Raut, S. Vishvakarma","doi":"10.1145/3526241.3530354","DOIUrl":"https://doi.org/10.1145/3526241.3530354","url":null,"abstract":"In the analog domain, with the increase in ReRAM m × n crossbar array, the Loading Effect (LE) seems to grow at the input of the comparator stage in analog to digital converter (ADC). The reference voltage generating ladder nodes for ADC are susceptible to design parameters due to small input voltages. We used the PMOS transistor to design this ladder circuitry. Further, sleep mode is applied using the power-gating (PG) technique to lower power dissipation. In this article, a Pareto study has been performed to evaluate robust and stable circuitry with minimum LE in the reference voltage ladder for ADC. An NMOS-based Current mirror is also designed and used with the proposed reference voltage ladder to achieve better stability in terms of power supply and reference voltage variations. Further, we analyzed the Process, Voltage, and Temperature (PVT) variation impact on the proposed circuitry. Finally, the power consumption of the proposed ladder at the 180nm technology node, is 0.7uW. Also, the circuit supports the power-gating technique in sleep mode, saving 43% of total power. Circuit's Monte-Carlo simulation for node voltage variation shows minimum mean and σ deviation. The circuit supports the power-gating technique in sleep mode, saving 43% of total power.","PeriodicalId":188228,"journal":{"name":"Proceedings of the Great Lakes Symposium on VLSI 2022","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123750189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Exploration into the Explainability of Neural Network Models for Power Side-Channel Analysis 电力侧信道分析中神经网络模型的可解释性探讨

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530346

Anupam Golder, Ashwin Bhat, A. Raychowdhury

引用次数: 4

Attack-Resistant Circuit Technologies for sub-5nm Secure Computing Platforms 亚5nm安全计算平台的抗攻击电路技术

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530053

S. Mathew

{"title":"Attack-Resistant Circuit Technologies for sub-5nm Secure Computing Platforms","authors":"S. Mathew","doi":"10.1145/3526241.3530053","DOIUrl":"https://doi.org/10.1145/3526241.3530053","url":null,"abstract":"Cryptographic hardware accelerators and root-of-trust circuits like True-Random-Number-Generators (TRNG) and Physically-Unclonable-Functions (PUF) have become essential components of present-day secure platforms. These circuits provide an on-die boundary within which users are given assurances that data privacy and integrity is preserved during computations and transport between storage and compute elements. The focus of hardware security engineers over the past many years has been in improving performance while reducing area and power consumption of cryptographic circuits. This tidy scenario was disrupted by a spate of attacks on computing platforms reported in the past few years. These attacks employed techniques such as speculative side-channels, physical (power/electromagnetic) side-channels, voltage/clock glitching and fault-injection to extract embedded secrets such as encryption keys or access privileged sections of system memory. The security community has responded to these attacks by launching research in resilient architectures and security circuits that are resistant to physical/machine-learning attacks. This talk will discuss attack-resistant encryption circuits for popular encryption workloads such as AES and RSA as well as describe PUF circuits that are resilient to powerful machine-learning attacks. While these circuits are shown to be secure against known attacks today, attackers are getting increasingly sophisticated with high resolution probes and employing advanced machine-learning techniques to subvert protection mechanisms. Security hardware designers are therefore engaged in an arms race of constantly outwitting malicious attackers while relying on continued research in energy-efficient attack-resistant security circuits.","PeriodicalId":188228,"journal":{"name":"Proceedings of the Great Lakes Symposium on VLSI 2022","volume":"352 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122846687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Data Stream Oriented Fine-grained Sparse CNN Accelerator with Efficient Unstructured Pruning Strategy 基于高效非结构化修剪策略的面向数据流的细粒度稀疏CNN加速器

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530318

Tianyang Yu, Bi Wu, Ke Chen, C. Yan, Weiqiang Liu

引用次数: 0

GAUR: Genetic Algorithm based Unlocking of Register Transfer Level Locking 基于遗传算法的寄存器传输级锁解锁

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530362

Gagan Gayari, C. Karfa, P. Guha

引用次数: 0

An Efficient Maze Routing Algorithm for Fast Global Routing 一种快速全局路由的高效迷宫路由算法

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530360

Zhaoqi Fu, Wenxin Yu, Jie Ma, Xin Cheng

引用次数: 0

AI/ML, Optimization and EDA in the TILOS AI Research Institute TILOS AI研究所的AI/ML，优化和EDA

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530052

A. Kahng

引用次数: 1

Securing On-chip Interconnect against Delay Trojan using Dynamic Adaptive Caging 使用动态自适应封装保护片上互连免受延迟木马攻击

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530333

Ruchika Gupta, Vedika J. Kulkarni, John Jose, Sukumar Nandi

{"title":"Securing On-chip Interconnect against Delay Trojan using Dynamic Adaptive Caging","authors":"Ruchika Gupta, Vedika J. Kulkarni, John Jose, Sukumar Nandi","doi":"10.1145/3526241.3530333","DOIUrl":"https://doi.org/10.1145/3526241.3530333","url":null,"abstract":"With the progressive innovation of VLSI technology, Tiled Chip Multicore Processors (TCMP) have surfaced up as the backbone of the modern data intensive parallel multi-core systems. Network-on-Chip (NoC) is considered as the most preferred choice for on-chip communication. Manufacturers have begun to investigate the prospects of using third-party IP in sophisticated TCMP designs due to strict time-to-market limitations. The inflated reliance over third party IPs induced security vulnerabilities in inter-tile communication. In this paper, we implement a novel Hardware Trojan (HT) called as Delay Trojan (DT) placed in an NoC router. Proposed DT adds random delay to flits going through it, while other NoC routers merely experience regular congestion, making DT detection difficult. As a result, packets of latency-critical applications stalls impacting system performance and throughput. Further, we propose a dynamic adaptive learning framework embedded in NoC routers that detects DT with reasonable accuracy and alerts neighboring routers. We also propose a caging technique to re-route packets. Our experimental study evaluates the impact of DT and the effectiveness of the proposed solution.","PeriodicalId":188228,"journal":{"name":"Proceedings of the Great Lakes Symposium on VLSI 2022","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129759210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Compaction of Compressed Bounded Transparent-Scan Test Sets 压缩有界透明扫描测试集的压缩

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530358

I. Pomeranz

引用次数: 0

CoSeP: Compression and Content-based Selection Procedure to Improve Lifetime of Encrypted Non-Volatile Main Memories 提高加密非易失性主存储器寿命的压缩和基于内容的选择程序

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530375

Arijit Nath, H. Kapoor

引用次数: 1