Compaction of Compressed Bounded Transparent-Scan Test Sets

Abstract

Bounded transparent-scan supports test compaction beyond that achievable with conventional scan-based tests. This article considers the compression of bounded transparent-scan tests. All the components of a test (scan-in state, primary input vector, scan-in and scan-enable sequences) are produced by the on-chip decompression logic from a compressed test. The article describes a test compaction procedure that starts from a conventional compressed and compacted multicycle scan-based test set. Such a test set benefits from test data compression and test compaction applicable to conventional scan-based tests. The procedure modifies as many tests as possible into compressed bounded transparent-scan tests to reduce the number of tests, the storage requirements, and the number of clock cycles required for test application. Experimental results for benchmark circuits demonstrate the ability to compress bounded transparent-scan tests and achieve test compaction.