Loading Effect Free MOS-only Voltage Reference Ladder for ADC in RRAM-crossbar Array

Abstract

In the analog domain, with the increase in ReRAM m × n crossbar array, the Loading Effect (LE) seems to grow at the input of the comparator stage in analog to digital converter (ADC). The reference voltage generating ladder nodes for ADC are susceptible to design parameters due to small input voltages. We used the PMOS transistor to design this ladder circuitry. Further, sleep mode is applied using the power-gating (PG) technique to lower power dissipation. In this article, a Pareto study has been performed to evaluate robust and stable circuitry with minimum LE in the reference voltage ladder for ADC. An NMOS-based Current mirror is also designed and used with the proposed reference voltage ladder to achieve better stability in terms of power supply and reference voltage variations. Further, we analyzed the Process, Voltage, and Temperature (PVT) variation impact on the proposed circuitry. Finally, the power consumption of the proposed ladder at the 180nm technology node, is 0.7uW. Also, the circuit supports the power-gating technique in sleep mode, saving 43% of total power. Circuit's Monte-Carlo simulation for node voltage variation shows minimum mean and σ deviation. The circuit supports the power-gating technique in sleep mode, saving 43% of total power.