2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献_第3页

Cache Partitioning + Loop Tiling: A Methodology for Effective Shared Cache Management 缓存分区+循环平铺:一种有效的共享缓存管理方法

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-03 DOI: 10.1109/ISVLSI.2017.89

Vasilios I. Kelefouras, G. Keramidas, N. Voros

引用次数: 2

Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects 使抽象模型上的故障注入成为预测RT-Level效应的更准确工具

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-03 DOI: 10.1109/ISVLSI.2017.99

Tino Flenker, Jan Malburg, G. Fey, Serhiy Avramenko, M. Violante, M. Reorda

{"title":"Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects","authors":"Tino Flenker, Jan Malburg, G. Fey, Serhiy Avramenko, M. Violante, M. Reorda","doi":"10.1109/ISVLSI.2017.99","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.99","url":null,"abstract":"Fault injection and fault simulation are a typical approach to analyze the effect of a fault on a hardware/software system. Often fault injection is done on abstract models of the system either to retrieve early results when no implementation is available, yet, or to speed-up the runtime intensive fault simulation on detailed models. The simulation results from the abstract model are typically inaccurate because details of the concrete hardware are missing.Here, we propose an approach to relate faults from an abstract untimed algorithmic model to their counterparts in the concrete register transfer models. This allows to understand which faults are covered on the concrete model and to speed up the fault simulation process.We use a mapping between both models' variables and mapped timing states for fault injection to corresponding variables on both models. After fault simulations the results are compared to check, whether a given fault produces the same behavior on both models. The results show that an injected fault to corresponding variables leads to the same behavior of both models for a large share of faults.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130790060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

AICNN: Implementing Typical CNN Algorithms with Analog-to-Information Conversion Architecture AICNN:用模拟-信息转换架构实现典型的CNN算法

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-03 DOI: 10.1109/ISVLSI.2017.23

Kaige Jia, Zheyu Liu, F. Qiao, Xinjun Liu, Qi Wei, Huazhong Yang

{"title":"AICNN: Implementing Typical CNN Algorithms with Analog-to-Information Conversion Architecture","authors":"Kaige Jia, Zheyu Liu, F. Qiao, Xinjun Liu, Qi Wei, Huazhong Yang","doi":"10.1109/ISVLSI.2017.23","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.23","url":null,"abstract":"AICNN architecture is presented in this work to map the state-of-the-art machine-learning algorithms of CNN to power-constrained embedded hardware. As the combination of analog-to-information conversion and typical CNN algorithms, AICNN can realize ultra-highly efficient computation by using massive parallel analog signal processing circuits, which could also significantly reduce ADC devices cost of converting sensors' outputs. As a design example, the specific AICNN-3 implementation is evaluated, which realize the minimum system of typical CNN task using AICNN architecture, with SMIC 0.18 µm CMOS process. Simulation results show that the AICNN-3 can classify a 28x28 MNIST image with only 1.47nJ. Compared with baseline implementation on CPU, the AICNN-3 could achieve 67000x energy-efficiency improvement, however the accuracy loss is less than 1%. Moreover, the influences of devices mismatch and process variations are evaluated using Monte Carlo statistical method, for the imperfection of analog processing paradigm, as well as the scalability of AICNN architecture is also discussed.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130280300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A Fully Integrated Fast-Response LDO Voltage Regulator with Adaptive Transient Current Distribution 具有自适应瞬态电流分布的全集成快速响应LDO稳压器

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-03 DOI: 10.1109/ISVLSI.2017.93

X. Tong, Kang Wei

引用次数: 12

Centrality Indicators for Efficient and Scalable Logic Masking 高效可扩展逻辑屏蔽的中心性指标

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-03 DOI: 10.1109/ISVLSI.2017.26

Brice Colombier, L. Bossuet, D. Hély

{"title":"Centrality Indicators for Efficient and Scalable Logic Masking","authors":"Brice Colombier, L. Bossuet, D. Hély","doi":"10.1109/ISVLSI.2017.26","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.26","url":null,"abstract":"Modifying the logic at register transfer level can help to protect a circuit against counterfeiting or illegal copying. By adding extra gates, the outputs can be controllably corrupted. Then the circuit operates correctly only if the right value is applied to the extra gates. The main challenge is to select the best position for these gates, to alter the circuit's behaviour as much as possible. However, another major point is the computational efficiency of the selection process, which should be as good as possible for integration in EDA tools. State-of-the art methods, based on fault analysis, are very demanding and cannot cope with large netlists in a reasonable runtime. We propose to use centrality indicators instead. Centrality is used to identify the most significant vertices of a graph. We show that, when used to select the nodes to modify, they lead to low correlation between original and altered outputs while being computationally efficient. We give experimental results on combinational benchmarks and compare to other previously proposed heuristics. We show that this method is the only efficient selection heuristic which is able to handle large netlists and integrate smoothly into EDA tools.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129740279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

High Speed Power Efficient Carry Select Adder Design 高速功率高效进位选择加法器设计

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-03 DOI: 10.1109/ISVLSI.2017.16

Raghava Katreepalli, T. Haniotakis

引用次数: 15

SiLago-CoG: Coarse-Grained Grid-Based Design for Near Tape-Out Power Estimation Accuracy at High Level SiLago-CoG:基于粗粒度网格的高水平近带出功率估计精度设计

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-03 DOI: 10.1109/ISVLSI.2017.15

Syed M. A. H. Jafri, Nasim Farahini, A. Hemani

{"title":"SiLago-CoG: Coarse-Grained Grid-Based Design for Near Tape-Out Power Estimation Accuracy at High Level","authors":"Syed M. A. H. Jafri, Nasim Farahini, A. Hemani","doi":"10.1109/ISVLSI.2017.15","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.15","url":null,"abstract":"It is well known that ASICs have orders of magnitude higher power efficiency than general propose processors. However, due to the high engineering and manufacturing cost only handful of companies can afford to design ASICs. To reduce this cost numerous high-level synthesis tools have emerged since last 2-3 decades. In spite of these tools, ASIC design is still considered expensive because they fail to accurately predict the cost metrics. The inaccuracy is costly as it results in multiple iterations between RTL, logic synthesis, and physical design. The major reason behind this inaccuracy, at high level, is unavailability of information like wiring, orientation, and placement of hardware blocks. To tackle this issue, recent works have proposed to raise the abstraction of the physical design from standard cells to micro-architectural blocks physically organized in a structured grid based layout scheme. While these works have been successful in accurately predicting area and timing, to the best of our knowledge their effectiveness in accurately estimating power is yet to be determined. SiLago-CoG provides an efficient technique to characterize these blocks and estimate power at high level. Simulation and synthesis results reveal that SiLago-CoG provides up to 15X better power estimates in 680X less time at the cost of up to 50% additional area, compared to state-of-the-art.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129982916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Voltage Noise Analysis with Ring Oscillator Clocks 环形振荡器时钟的电压噪声分析

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-03 DOI: 10.1109/ISVLSI.2017.11

Lucas Machado, A. Perez, J. Cortadella

引用次数: 4

Resilient Cell-Based Architecture for Time-to-Digital Converter 基于弹性单元的时间-数字转换器结构

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-03 DOI: 10.1109/ISVLSI.2017.12

Chia-Hua Wu, Shi-Yu Huang, Mason Chern, Yung-Fa Chou, D. Kwai

引用次数: 7

Sample Preparation on Micro-Electrode-Dot-Array Digital Microfluidic Biochips 微电极点阵列数字微流控生物芯片的样品制备

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-03 DOI: 10.1109/ISVLSI.2017.34

Zipeng Li, Kelvin Yi-Tse Lai, K. Chakrabarty, Tsung-Yi Ho, Chen-Yi Lee

引用次数: 16