2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献_第10页

Customizing Skewed Trees for Fast Memory Integrity Verification in Embedded Systems 自定义倾斜树用于嵌入式系统中快速内存完整性验证

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-01 DOI: 10.1109/ISVLSI.2017.45

Saru Vig, Tan Yng Tzer, Guiyuan Jiang, S. Lam

{"title":"Customizing Skewed Trees for Fast Memory Integrity Verification in Embedded Systems","authors":"Saru Vig, Tan Yng Tzer, Guiyuan Jiang, S. Lam","doi":"10.1109/ISVLSI.2017.45","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.45","url":null,"abstract":"Memory integrity in embedded systems has been a longstanding issue in trusted system design. Existing schemes perform runtime integrity verification using memory integrity trees in order to secure untrusted external memories from malicious attacks e.g. replay, spoofing, and splicing. However, the balanced memory integrity trees used in existing approaches lead to excessive memory access overheads during runtime verification. In this paper, we proposed a framework to construct customized integrity trees based on the memory access patterns of the application. The framework relies on an offline process to analyze the frequency of data accesses and utilizes the package merge algorithm to generate a skewed memory integrity tree based on the frequency pattern. To the best of our knowledge, our work is the first to propose an automated approach for generating customized memory integrity trees. We validated the effectiveness of our approach on the Altera NIOS II processor with an external DRAM. Experimental results based on applications from widely used CHStone and SNU Real-Time benchmarks demonstrated that the proposed approach can lead to an average performance gain of 18% compared to the case where balanced memory integrity trees is used. To provide for further performance improvement in integrity tree verification, we implemented the encryption/decryption operation using custom instructions on the NIOS II processor. This resulted in an additional 10x performance improvement for the applications considered.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130047388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Low Power Implantable Spike Sorting Scheme Based on Neuromorphic Classifier with Supervised Training Engine 基于监督训练引擎的神经形态分类器低功耗可植入尖峰分类方案

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-01 DOI: 10.1109/ISVLSI.2017.54

Rakshit Pathak, Saurav Dash, Anand Kumar Mukhopadhyay, A. Basu, M. Sharad

{"title":"Low Power Implantable Spike Sorting Scheme Based on Neuromorphic Classifier with Supervised Training Engine","authors":"Rakshit Pathak, Saurav Dash, Anand Kumar Mukhopadhyay, A. Basu, M. Sharad","doi":"10.1109/ISVLSI.2017.54","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.54","url":null,"abstract":"An ultra-low power neural spike sorting technique for implantable, multi-channel neural implant is proposed. It involves spiking neural network (SNN) with binary weights as an energy and area efficient classifier, along with a suitable frontend for spike encoding of the recorded neuro-potential. The proposed scheme employs two step training to implement supervised learning for the classifier, in order to achieve appreciable classification accuracy, along with low power dissipation. During the 1st phase a k-mean clustering module is trained with the real-time input data. In the 2nd phase, the trained means are used to perform supervised learning for the SNN classifier. After the training process, the low power SNN module is used for the classification task. In the proposed scheme, the K-means training module can be shared among large number of channels for training the dedicated SNN modules, which are relatively compact and can operate with ±4x lower power (as compared to the K-means sorter), while preserving the classification accuracy. Algorithm and architecture level optimizations for the proposed system are presented.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126707754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Secured-by-Design FPGA against Early Evaluation 针对早期评估的设计安全FPGA

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-01 DOI: 10.1109/ISVLSI.2017.44

Z. Almohaimeed, M. Sima

引用次数: 0

Design of an Asynchronous Detector with Priority Encoding Technique 采用优先编码技术的异步检测器设计

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-01 DOI: 10.1109/ISVLSI.2017.98

Keunyeol Park, Oh-Sang Kwon, H. Noh, Minhyun Jin, Minkyu Song

引用次数: 0

On Benchmarking Pin Access for Nanotechnology Standard Cells 纳米技术标准电池引脚通路的基准测试

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-01 DOI: 10.1109/ISVLSI.2017.49

Shang-Rong Fang, Cheng-Wei Tai, Rung-Bin Lin

引用次数: 5

Project HIPNOS: Case Study of High Performance Avionics for Active Debris Removal in Space HIPNOS项目:用于空间主动碎片清除的高性能航空电子设备案例研究

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-01 DOI: 10.1109/ISVLSI.2017.68

G. Lentaris, I. Stratakos, I. Stamoulias, Konstantinos Maragos, D. Soudris, Manolis I. A. Lourakis, Xenophon Zabulis, D. Gonzalez-Arjona

{"title":"Project HIPNOS: Case Study of High Performance Avionics for Active Debris Removal in Space","authors":"G. Lentaris, I. Stratakos, I. Stamoulias, Konstantinos Maragos, D. Soudris, Manolis I. A. Lourakis, Xenophon Zabulis, D. Gonzalez-Arjona","doi":"10.1109/ISVLSI.2017.68","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.68","url":null,"abstract":"The Clean Space initiative of the European Space Agency (ESA) seeks to decrease the environmental impact of space programmes by focusing, among others, on Active Debris Removal (ADR) and eDeorbit. In this direction, one of the main challenges is to autonomously track and approach a big non-cooperative satellite such as ENVISAT. To achieve the high level of autonomy required in this phase of the ADR mission, vision based navigation will guide a chaser spacecraft in real-time based on high-definition images acquired and processed on-board at high frame-rates. The increased complexity of these computer vision algorithms mandates the development and use of high performance avionics to provide one order of magnitude faster execution than today's conventional space-grade processors. In the context of ESA's project HIPNOS (HIgh Performance avionics solutioN for advanced and complex GNC Systems), we study algorithms and avionics architectures suitable for ADR. The examined algorithms base on image feature extraction and the architectures base on COTS SoC-FPGA devices. Preliminary analysis highlights the benefits of employing this avionics solution in future space missions.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125594649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Parallel Simulation-Based Verification of RC Power Grids 基于并联仿真的RC电网验证

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-01 DOI: 10.1109/ISVLSI.2017.84

M. Fawaz, F. Najm

引用次数: 3

An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem 基于LUT合并定理的fpga乘法器的高效设计

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-01 DOI: 10.1109/ISVLSI.2017.29

Zarrin Tasnim Sworna, Mubin Ul Haque, H. Babu, Lafifa Jamal, A. Biswas

{"title":"An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem","authors":"Zarrin Tasnim Sworna, Mubin Ul Haque, H. Babu, Lafifa Jamal, A. Biswas","doi":"10.1109/ISVLSI.2017.29","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.29","url":null,"abstract":"FPGA (Field Programmable gate array) technology has become an integral part of todays modern embedded systems. All mainstream commercial FPGA devices are based upon LUT (Look-up Table) structures. As any m-input Boolean function can be implemented using m-input LUTs, it is a prime concern to reduce the number of LUTs while implementing an FPGA-based circuit for given functions. In this paper, a LUT merging theorem is proposed, which reduces the required number of LUTs for the implementation of a set of functions by a factor of two. The proposed LUT merging theorem performs selection, partition and merging of the LUTs to reduce the area. Using the proposed LUT merging theorem, an (1x1)-digit multiplication algorithm is proposed, which does not require any partial product generation, partial product reduction and addition steps. An (1 × 1)—digit multiplication algorithm is proposed which performs digit-wise parallel processing and provides a significant reduction in carry propagation delay. The proposed multiplier circuit is 49.93% and 34.9% efficient than the existing best one in terms of required number of LUTs and delay, respectively for (8 x8)- digit multiplication.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114437849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Performing Mathematics Using DNA: Complex Number Arithmetic Using Sticker Model 使用DNA执行数学:使用贴纸模型的复数算术

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-01 DOI: 10.1109/ISVLSI.2017.105

Mayukh Sarkar, P. Ghosal

{"title":"Performing Mathematics Using DNA: Complex Number Arithmetic Using Sticker Model","authors":"Mayukh Sarkar, P. Ghosal","doi":"10.1109/ISVLSI.2017.105","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.105","url":null,"abstract":"DNA Computing, since its inception in 1994, has caught the eyes of researchers due to its massive parallelism and extremely high data density. These powers have given DNA Computer the ability to solve computationally \"hard\" problems using search over large search space, as well as a powerful data storage technique. This would be much more powerful and general purpose when its ability is increased to solve general-purpose problems too, which can be solved easily on a conventional computer. As an example, DNA Computing falls short in mathematical computations, such as performing simple arithmetic as well as complex number arithmetic etc. In this work, the major purpose is to increase the power of DNA Computing to solve such general purpose problems. This work attempts to perform complex number arithmetic, such as addition, subtraction, multiplication, and division of two complex numbers. True to the best of authors knowledge, no work has been performed to perform representation and arithmetic of complex numbers using DNA molecules. This work has several advantages, such as bio-molecular operations being used here are easy to implement, and operations can be carried out on arbitrarily large numbers.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122655421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Ultra High Throughput Unrolled Layered Architecture for QC-LDPC Decoders 用于QC-LDPC解码器的超高吞吐量展开分层架构

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-01 DOI: 10.1109/ISVLSI.2017.47

O. Boncalo, A. Amaricai

引用次数: 10