An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem

Abstract

FPGA (Field Programmable gate array) technology has become an integral part of todays modern embedded systems. All mainstream commercial FPGA devices are based upon LUT (Look-up Table) structures. As any m-input Boolean function can be implemented using m-input LUTs, it is a prime concern to reduce the number of LUTs while implementing an FPGA-based circuit for given functions. In this paper, a LUT merging theorem is proposed, which reduces the required number of LUTs for the implementation of a set of functions by a factor of two. The proposed LUT merging theorem performs selection, partition and merging of the LUTs to reduce the area. Using the proposed LUT merging theorem, an (1x1)-digit multiplication algorithm is proposed, which does not require any partial product generation, partial product reduction and addition steps. An (1 × 1)—digit multiplication algorithm is proposed which performs digit-wise parallel processing and provides a significant reduction in carry propagation delay. The proposed multiplier circuit is 49.93% and 34.9% efficient than the existing best one in terms of required number of LUTs and delay, respectively for (8 x8)- digit multiplication.