2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献

A Power Delivery Network and Cell Placement Aware IR-Drop Mitigation Technique: Harvesting Unused Timing Slacks to Schedule Useful Skews 电力输送网络和小区放置感知ir下降缓解技术:收集未使用的时间松弛来调度有用的倾斜

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-10-03 DOI: 10.1109/ISVLSI.2017.55

Lakshmi Bhamidipati, B. Gunna, H. Homayoun, Avesta Sasan

引用次数: 11

Assessing Self-Repair on FPGAs with Biologically Realistic Astrocyte-Neuron Networks 利用星形细胞-神经元网络评估fpga的自我修复

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-20 DOI: 10.1109/ISVLSI.2017.80

Shvan Karim, J. Harkin, L. McDaid, B. Gardiner, Junxiu Liu, D. Halliday, A. Tyrrell, J. Timmis, Alan G. Millard, Anju P. Johnson

{"title":"Assessing Self-Repair on FPGAs with Biologically Realistic Astrocyte-Neuron Networks","authors":"Shvan Karim, J. Harkin, L. McDaid, B. Gardiner, Junxiu Liu, D. Halliday, A. Tyrrell, J. Timmis, Alan G. Millard, Anju P. Johnson","doi":"10.1109/ISVLSI.2017.80","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.80","url":null,"abstract":"This paper presents a hardware based implementation of a biologically-faithful astrocyte-based selfrepairing mechanism for Spiking Neural Networks. Spiking Astrocyte-neuron Networks (SANNs) are a new computing paradigm which capture the key mechanisms of how the human brain performs repairs. Using SANN in hardware affords the potential for realizing computing architecture that can self-repair. This paper demonstrates that Spiking Astrocyte Neural Network (SANN) in hardware have a resilience to significant levels of faults. The key novelty of the paper resides in implementing an SANN on FPGAs using fixed-point representation and demonstrating graceful performance degradation to different levels of injected faults via its self-repair capability. A fixed-point implementation of astrocyte, neurons and tripartite synapses are presented and compared against previous hardware floating-point and Matlab software implementations of SANN. All results are obtained from the SANN FPGA implementation and show how the reduced fixedpoint representation can maintain the biologically-realistic repair capability","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131119521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

AEGLE's Cloud Infrastructure for Resource Monitoring and Containerized Accelerated Analytics AEGLE的用于资源监控和容器化加速分析的云基础设施

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-20 DOI: 10.1109/ISVLSI.2017.70

Konstantina Koliogeorgi, Dimosthenis Masouros, Georgios Zervakis, S. Xydis, Tobias Becker, G. Gaydadjiev, D. Soudris

{"title":"AEGLE's Cloud Infrastructure for Resource Monitoring and Containerized Accelerated Analytics","authors":"Konstantina Koliogeorgi, Dimosthenis Masouros, Georgios Zervakis, S. Xydis, Tobias Becker, G. Gaydadjiev, D. Soudris","doi":"10.1109/ISVLSI.2017.70","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.70","url":null,"abstract":"This paper presents the cloud infrastructure of the AEGLE project, that targets to integrate cloud technologies together with heterogeneous reconfigurable computing in large scale healthcare systems for Big Bio-Data analytics. AEGLEs engineering concept brings together the hot big-data engines with emerging acceleration technologies, putting the basis for personalized and integrated health-care services, while also promoting related research activities. We introduce the design of AEGLE’s accelerated infrastructure along with the corresponding software and hardware acceleration stacks to support various big data analytics workloads showing that through effective resource containerization AEGLE’s cloud infrastructure is able to support high heterogeneity regarding to storage types, execution engines, utilized tools and execution platforms. Special care is given to the integration of high performance accelerators within the overall software stack of AEGLE’s infrastructure, which enable efficient execution of analytics, up to 140× according to our preliminary evaluations, over pure software executions.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131572647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

On Tolerating Faults of TSV/Microbumps for Power Delivery Networks in 3D IC 三维集成电路输电网TSV/微凸点容错研究

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-20 DOI: 10.1109/ISVLSI.2017.86

Sheng-Hsin Fang, Chang-Tzu Lin, Wei-Hsun Liao, Chien-Chia Huang, Li-Chin Chen, Hung-Ming Chen, I-Hsuan Lee, D. Kwai, Yung-Fa Chou

引用次数: 1

Area and Delay Efficient Design of a Quantum Bit String Comparator 量子比特串比较器的面积和延迟效率设计

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-03 DOI: 10.1109/ISVLSI.2017.130

H. Babu, Lafifa Jamal, S. V. Dibbo, A. Biswas

引用次数: 2

Architecting SOT-RAM Based GPU Register File 基于SOT-RAM的GPU寄存器文件架构

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-03 DOI: 10.1109/ISVLSI.2017.17

Sparsh Mittal, R. Bishnoi, Fabian Oboril, Haonan Wang, M. Tahoori, Adwait Jog, J. Vetter

引用次数: 6

Capacitor Mismatch Calibration Technique to Improve the SFDR of 14-Bit SAR ADC 提高14位SAR ADC SFDR的电容失配校准技术

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-03 DOI: 10.1109/ISVLSI.2017.97

Hua Fan, F. Maloberti, Dagang Li, Daqian Hu, Yuanjun Cen, H. Heidari

引用次数: 4

Detection of Layout-Level Trojans by Monitoring Substrate with Preexisting Built-in Sensors 利用预先存在的内置传感器监测基板检测布局级木马

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-03 DOI: 10.1109/ISVLSI.2017.58

Leonel Acunha Guimaraes, R. P. Bastos, L. Fesquet

引用次数: 8

A Multi-Gbps Fully Pipelined Layered Decoder for IEEE 802.11n/ac/ax LDPC Codes IEEE 802.11n/ac/ax LDPC码的多gbps全流水线分层解码器

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-03 DOI: 10.1109/ISVLSI.2017.42

Saleh Usman, Mohammad M. Mansour, A. Chehab

{"title":"A Multi-Gbps Fully Pipelined Layered Decoder for IEEE 802.11n/ac/ax LDPC Codes","authors":"Saleh Usman, Mohammad M. Mansour, A. Chehab","doi":"10.1109/ISVLSI.2017.42","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.42","url":null,"abstract":"This paper presents a fully pipelined layered decoder architecture for IEEE 802.11 n/ac/ax LDPC codes, free of idle cycles. Several decoder architectures for such codes have emerged in the literature featuring throughputs in the multi- Gbps range. The proposed architecture surpasses the highest reported throughput for IEEE 802.11 n/ac/ax LDPC codes. This is achieved 1) algorithmically, by implementing the layered LDPC decoding schedule, and 2) architecturally, by optimizing register-based memories for IEEE 802.11n/ac LDPC codes and implementing an idle-cycle-free pipelined single-codeword datapath decoder. Register-based memories provide full bandwidth access to read and write all messages of a layer in one clock cycle. Single-codeword processing in the datapath significantly reduces memory overhead compared to other architectures that process multiple codewords to boost throughput at the expense of a larger footprint. The proposed architecture is synthesized in 40 nm CMOS process for IEEE 802.11 n/ac, rate 1/2 LDPC codes. The decoder occupies an area of 0.38 mm2, runs at a frequency of 780 MHz, and achieves a throughput of 4.2 Gbps.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128100127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

STBC: Side Channel Attack Tolerant Balanced Circuit with Reduced Propagation Delay STBC:具有减少传播延迟的侧信道容错平衡电路

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-03 DOI: 10.1109/ISVLSI.2017.22

Hyunmin Kim, Seokhie Hong, B. Preneel, I. Verbauwhede

引用次数: 8