STBC: Side Channel Attack Tolerant Balanced Circuit with Reduced Propagation Delay

Abstract

Side channel attacks exploit the physical properties of integrated circuits to extract sensitive information. They are becoming increasingly important in the context of the deployment of the Internet of Things. One of the most effective countermeasures consists of modifying the logic circuits to reduce the leakage through side channels. This paper presents a novel side channel attack tolerant balanced circuit (STBC) based on a dynamic and differential configuration. Its main feature is the use of an improved binary decision diagram (BDD) with a multi-output function and internal gate sharing to reduce the implementation area. Compared to the earlier proposed dual-rail pre-charge circuit with binary decision diagram (DP-BDD) technique, an area reduction of 13.7% is achieved. A fixed versus random t-test shows that STBC obtains a substantial reduction in information leakage even though small peak exists. Further, its input variable dependence is comparable with that of a normal CMOS circuit and similar with DP-BDD.