2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献_第2页

Scouting Logic: A Novel Memristor-Based Logic Design for Resistive Computing 侦察逻辑:一种新的基于忆阻器的电阻计算逻辑设计

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-03 DOI: 10.1109/ISVLSI.2017.39

Lei Xie, Hoang Anh Du Nguyen, Jintao Yu, A. Kaichouhi, M. Taouil, M. Alfailakawi, S. Hamdioui

{"title":"Scouting Logic: A Novel Memristor-Based Logic Design for Resistive Computing","authors":"Lei Xie, Hoang Anh Du Nguyen, Jintao Yu, A. Kaichouhi, M. Taouil, M. Alfailakawi, S. Hamdioui","doi":"10.1109/ISVLSI.2017.39","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.39","url":null,"abstract":"Memristor technology is a promising alternative to CMOS due to its high integration density, near-zero standby power, and ability to implement novel resistive computing. One of the major limitations of these architectures is the limited endurance of memristor devices, especially when a logic gate requires multiple steps/switching to execute the logic operations. To alleviate the endurance requirement and improve the performance, we present a novel logic design style, called scouting logic that executes any logic gate by only reading the memristor devices and without changing their states. Hence, no impact on the memristors' endurance. The proposed design is implemented using two styles (current and voltage based). To illustrate the performance of scouting logic based designs, the area, delay, and power consumption are analyzed and compared with state-ofthe- art. The results show that scouting logic improves the delay and power consumption by at least a factor of 2.3, while having similar or less area overhead. Finally, we discuss the potential applications and challenges of scouting logic.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129733606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 86

Unified Model for Contrast Enhancement and Denoising 对比度增强和去噪的统一模型

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-03 DOI: 10.1109/ISVLSI.2017.73

A. P. James, O. Krestinskaya, J. Mathew

引用次数: 4

Unconventional Layout Techniques for a High Performance, Low Variability Subthreshold Standard Cell Library 用于高性能、低可变性亚阈值标准单元库的非常规布局技术

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-03 DOI: 10.1109/ISVLSI.2017.14

Jordan Morris, Pranay Prabhat, James Myers, A. Yakovlev

引用次数: 15

Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack Via 利用高密度叠间通孔改进FPGA单片三维集成设计

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-03 DOI: 10.1109/ISVLSI.2017.31

S. Srinivasa, K. Mohan, Wei-Hao Chen, Kuo-Hsiang Hsu, Xueqing Li, Meng-Fan Chang, S. Gupta, J. Sampson, N. Vijaykrishnan

引用次数: 6

Hybrid Polymorphic Logic Gate with 5-Terminal Magnetic Domain Wall Motion Device 具有五端磁畴壁运动装置的混合多晶逻辑门

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-03 DOI: 10.1109/ISVLSI.2017.35

Farhana Parveen, Zhezhi He, Shaahin Angizi, Deliang Fan

引用次数: 25

Hardware Acceleration for Machine Learning 机器学习的硬件加速

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-03 DOI: 10.1109/ISVLSI.2017.127

Ruizhe Zhao, W. Luk, Xinyu Niu, Huifeng Shi, Haitao Wang

引用次数: 26

Analysis of RRAM Reliability Soft-Errors on the Performance of RRAM-Based Neuromorphic Systems RRAM可靠性软误差对基于RRAM的神经形态系统性能影响分析

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-03 DOI: 10.1109/ISVLSI.2017.20

Amr M. S. Tosson, Shimeng Yu, M. Anis, Lan Wei

{"title":"Analysis of RRAM Reliability Soft-Errors on the Performance of RRAM-Based Neuromorphic Systems","authors":"Amr M. S. Tosson, Shimeng Yu, M. Anis, Lan Wei","doi":"10.1109/ISVLSI.2017.20","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.20","url":null,"abstract":"Due to the limitation in speed and throughput of the traditional Von Neumann architecture, the interest in braininspired neuromorphic systems has been the focus of recent research activities. RRAM device has been extensively used as synapses in neuromorphic systems due to its many advantages including small size and compatibility with CMOS fabrication process. However, the RRAM device suffers from reliability soft-errors resulting from the stochastic nature of the oxygen vacancies of its conductive filaments. In this article, for the first time, using a combination of SPICE-based and BRIAN-based simulations, a novel framework is developed to model and assess the impact of RRAM reliability soft-errors on the performance of the neuromorphic systems. Simulation results show that the accuracy of a multi-perceptron RRAM-based neuromorphic system drops from 91.6% to 43% when the reliability softerrors are considered. To overcome this degradation in the system performance, a detailed analysis is conducted to modify the way the RRAM resistive state changes. In addition to this, a list of recommendations for the design of neuromorphic systems is also provided to overcome the RRAM reliability soft-errors.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133695304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

RIMPA: A New Reconfigurable Dual-Mode In-Memory Processing Architecture with Spin Hall Effect-Driven Domain Wall Motion Device RIMPA:一种新的可重构双模内存处理架构，具有自旋霍尔效应驱动的畴壁运动器件

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-03 DOI: 10.1109/ISVLSI.2017.18

Shaahin Angizi, Zhezhi He, Farhana Parveen, Deliang Fan

引用次数: 29

GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack GREAT:使用多功能标准化堆栈的异质集成磁性技术

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-03 DOI: 10.1109/ISVLSI.2017.67

M. Tahoori, S. Nair, R. Bishnoi, S. Senni, Jad Mohdad, F. Mailly, L. Torres, P. Benoit, P. Nouet, R. Ma, M. Kreissig, F. Ellinger, K. Jabeur, P. Vanhauwaert, G. D. Pendina, G. Prenat

{"title":"GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack","authors":"M. Tahoori, S. Nair, R. Bishnoi, S. Senni, Jad Mohdad, F. Mailly, L. Torres, P. Benoit, P. Nouet, R. Ma, M. Kreissig, F. Ellinger, K. Jabeur, P. Vanhauwaert, G. D. Pendina, G. Prenat","doi":"10.1109/ISVLSI.2017.67","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.67","url":null,"abstract":"To tackle the key issues of monolithic heterogeneous integration, fast yet low power processing, high integration density, fast yet low power storage, the goal of the GREAT project is to co-integrate multiple functions like sensors (“Sensing”), RF receivers (“Communicating”) and logic/memory (“Processing/Storing”) together within CMOS by adapting the STT-MTJs (Magnetic devices) to a single baseline technology enabling logic, memory, and analog functions in the same System-on-Chip (SoC) as the enabling technology platform for Internet of Things (IoT). This will lead to a unique STT-MTJ cell technology called Multifunctional Standardized Stack (MSS). The major outputs of GREAT are the technology and the architecture platform for IoT SoCs providing better integration of embedded & mobile communication systems and a significant decrease of their power consumption. Based on the STT-MTJs (now viewed as the most suitable technology for digital applications and with a huge potential for analog subsystems) unique set of performances (non-volatility, high speed, infinite endurance and moderate read/write power), GREAT will achieve the same goal as heterogeneous integration of devices but in a much simpler way since the MSS will enable different functions using the same technology.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"444 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116513825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap 机器学习的自适应和节能架构:挑战、机遇和研究路线图

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-03 DOI: 10.1109/ISVLSI.2017.124

M. Shafique, R. Hafiz, M. Javed, Sarmad Abbas, L. Sekanina, Z. Vašíček, Vojtěch Mrázek

{"title":"Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap","authors":"M. Shafique, R. Hafiz, M. Javed, Sarmad Abbas, L. Sekanina, Z. Vašíček, Vojtěch Mrázek","doi":"10.1109/ISVLSI.2017.124","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.124","url":null,"abstract":"Gigantic rates of data production in the era of Big Data, Internet of Thing (IoT) / Internet of Everything (IoE), and Cyber Physical Systems (CSP) pose incessantly escalating demands for massive data processing, storage, and transmission while continuously interacting with the physical world under unpredictable, harsh, and energy-/power-constrained scenarios. Therefore, such systems need to support not only the high performance capabilities at tight power/energy envelop, but also need to be intelligent/cognitive, self-learning, and robust. As a result, a hype in the artificial intelligence research (e.g., deep learning and other machine learning techniques) has surfaced in numerous communities. This paper discusses the challenges and opportunities for building energy-efficient and adaptive architectures for machine learning. In particular, we focus on brain-inspired emerging computing paradigms, such as approximate computing; that can further reduce the energy requirements of the system. First, we guide through an approximate computing based methodology for development of energy-efficient accelerators, specifically for convolutional Deep Neural Networks (DNNs). We show that in-depth analysis of datapaths of a DNN allows better selection of Approximate Computing modules for energy-efficient accelerators. Further, we show that a multi-objective evolutionary algorithm can be used to develop an adaptive machine learning system in hardware. At the end, we summarize the challenges and the associated research roadmap that can aid in developing energy-efficient and adaptable hardware accelerators for machine learning.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126492969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 39