Jordan Morris, Pranay Prabhat, James Myers, A. Yakovlev
{"title":"Unconventional Layout Techniques for a High Performance, Low Variability Subthreshold Standard Cell Library","authors":"Jordan Morris, Pranay Prabhat, James Myers, A. Yakovlev","doi":"10.1109/ISVLSI.2017.14","DOIUrl":null,"url":null,"abstract":"A novel subthreshold sizing strategy utilizing the Inverse Narrow Width Effect is demonstrated that has the largest range of propagation delays within the same cell footprint and lowest variability of any subthreshold sizing strategy thus far proposed. Simulation results and ring oscillators implemented in a commercial 65nm low power process confirm a propagation delay improvement of up to 1.95X over the standard superthreshold sizing strategy at 300mV and below. 32 bit multipliers are then synthesized and static timing analysis performed at several subthreshold voltage corners to illustrate applicability to real designs in conventional EDA design flows.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2017.14","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 15
Abstract
A novel subthreshold sizing strategy utilizing the Inverse Narrow Width Effect is demonstrated that has the largest range of propagation delays within the same cell footprint and lowest variability of any subthreshold sizing strategy thus far proposed. Simulation results and ring oscillators implemented in a commercial 65nm low power process confirm a propagation delay improvement of up to 1.95X over the standard superthreshold sizing strategy at 300mV and below. 32 bit multipliers are then synthesized and static timing analysis performed at several subthreshold voltage corners to illustrate applicability to real designs in conventional EDA design flows.