Ruizhe Zhao, W. Luk, Xinyu Niu, Huifeng Shi, Haitao Wang
{"title":"机器学习的硬件加速","authors":"Ruizhe Zhao, W. Luk, Xinyu Niu, Huifeng Shi, Haitao Wang","doi":"10.1109/ISVLSI.2017.127","DOIUrl":null,"url":null,"abstract":"This paper presents an approach to enhance the performance of machine learning applications based on hardware acceleration. This approach is based on parameterised architectures designed for Convolutional Neural Network (CNN) and Support Vector Machine (SVM), and the associated design flow common to both. This approach is illustrated by two case studies including object detection and satellite data analysis. The potential of the proposed approach is presented.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"26","resultStr":"{\"title\":\"Hardware Acceleration for Machine Learning\",\"authors\":\"Ruizhe Zhao, W. Luk, Xinyu Niu, Huifeng Shi, Haitao Wang\",\"doi\":\"10.1109/ISVLSI.2017.127\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an approach to enhance the performance of machine learning applications based on hardware acceleration. This approach is based on parameterised architectures designed for Convolutional Neural Network (CNN) and Support Vector Machine (SVM), and the associated design flow common to both. This approach is illustrated by two case studies including object detection and satellite data analysis. The potential of the proposed approach is presented.\",\"PeriodicalId\":187936,\"journal\":{\"name\":\"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)\",\"volume\":\"33 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-07-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"26\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVLSI.2017.127\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2017.127","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents an approach to enhance the performance of machine learning applications based on hardware acceleration. This approach is based on parameterised architectures designed for Convolutional Neural Network (CNN) and Support Vector Machine (SVM), and the associated design flow common to both. This approach is illustrated by two case studies including object detection and satellite data analysis. The potential of the proposed approach is presented.