三维集成电路输电网TSV/微凸点容错研究

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-20 DOI:10.1109/ISVLSI.2017.86

Sheng-Hsin Fang, Chang-Tzu Lin, Wei-Hsun Liao, Chien-Chia Huang, Li-Chin Chen, Hung-Ming Chen, I-Hsuan Lee, D. Kwai, Yung-Fa Chou

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引用次数: 1

摘要

在3DIC设计中，我们可能会面临通过硅通孔(tsv)和微凸点的制造故障问题，这将导致功率输出不足，最终导致致命的功能错误。在这项工作中，我们提出了一个功率TSV/微碰撞容错方案来解决这个问题。首先，通过分析功率仿真结果，采用快速启发式方法预测给定故障率下的最坏ir降分布。接下来，我们使用增量修复方法来增强供电网络，直到达到给定的目标ir下降。实验结果表明，该方法对TSV/微碰撞DFM的输电网络增强是有效的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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On Tolerating Faults of TSV/Microbumps for Power Delivery Networks in 3D IC

In 3DIC design, we may face the problem in manufacturing faults of through silicon vias (TSVs) and microbumps, and it will cause insufficient power delivery and eventually result in fatal error of functioning. In this work, we propose a power TSV/microbump fault tolerance scheme to resolve this issue. First, we use a fast heuristic to predict the worst IR-drop distribution under a given faulty rate by analyzing power simulation results. Next, we use an incremental repair method to enhance power delivery network until reaching the given target IR-drop. The experimental results show that our methodology is effective in power delivery network enhancement in TSV/microbump DFM.

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来源期刊

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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