On Tolerating Faults of TSV/Microbumps for Power Delivery Networks in 3D IC

Abstract

In 3DIC design, we may face the problem in manufacturing faults of through silicon vias (TSVs) and microbumps, and it will cause insufficient power delivery and eventually result in fatal error of functioning. In this work, we propose a power TSV/microbump fault tolerance scheme to resolve this issue. First, we use a fast heuristic to predict the worst IR-drop distribution under a given faulty rate by analyzing power simulation results. Next, we use an incremental repair method to enhance power delivery network until reaching the given target IR-drop. The experimental results show that our methodology is effective in power delivery network enhancement in TSV/microbump DFM.