Secured-by-Design FPGA against Early Evaluation

Abstract

CMOS power dissipation has multiple components: switching, short-circuit, and static. In order to be robust to power attacks, digital logic should eliminate the relation between processed data and each and every power component. Other sources of side-channel information are glitches and the early evaluation of signals. We improve over our previous work and propose a Look-Up Table (LUT) with increased robustness to early evaluation attacks. The resulting secured-by-design FPGA LUT exhibits quadruple robustness to attacks based on dynamic power, static power, glitches, and early evaluation, whereas its architecture remains in line with commercial FPGAs. The silicon area penalty is light making the disclosed FPGA attractive to cryptoysystems developers.