2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献_第9页

Compact Modeling of Graphene Barristor for Digital Integrated Circuit Design 数字集成电路设计中石墨烯电阻器的紧凑建模

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-01 DOI: 10.1109/ISVLSI.2017.104

Zhou Zhao, Xinlu Chen, A. Srivastava, Lu Peng, S. Mohanty

引用次数: 0

Transistor Temperature Deviation Analysis in Monolithic 3D Standard Cells 单片三维标准电池晶体管温度偏差分析

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-01 DOI: 10.1109/ISVLSI.2017.100

M. Brocard, B. Mathieu, J. Colonna, C. Santos, C. Fenouillet-Béranger, C. Lu, G. Cibrario, L. Brunet, P. Batude, F. Andrieu, S. Thuries, O. Billoint

{"title":"Transistor Temperature Deviation Analysis in Monolithic 3D Standard Cells","authors":"M. Brocard, B. Mathieu, J. Colonna, C. Santos, C. Fenouillet-Béranger, C. Lu, G. Cibrario, L. Brunet, P. Batude, F. Andrieu, S. Thuries, O. Billoint","doi":"10.1109/ISVLSI.2017.100","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.100","url":null,"abstract":"This study focuses on temperature deviation during operation of transistors inside a monolithic 3D standard cell built on two tiers. Early assessment of this topic is crucial to manage circuit design and requires both steady-state and transient thermal analysis at transistor level. A representative 3D standard cell in 14nm FDSOI technology is considered, using intermediate Back-End-Of-Line (iBEOL) and top tier BEOL. Steady-state and transient power dissipations in NMOS and PMOS are extracted from SPICE simulations with variables such as output load capacitance and operating temperature. 3D thermal simulations are then performed to assess the impact of design parameters such as routing densities, thicknesses of iBEOL and BEOL, their number of metal layers and packaging techniques. Steady-state and transient thermal simulations enable precise analysis to correlate temperature deviation of transistors with these parameters. Design guidelines are provided to limit the temperature deviation between top and bottom tier which can reach 7°Celsius during circuit operations in the worst case","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128817136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies 超越cmos多数技术的逆变器传播和扇出约束

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-01 DOI: 10.1109/ISVLSI.2017.37

Eleonora Testa, O. Zografos, Mathias Soeken, A. Vaysset, M. Manfrini, R. Lauwereins, G. Micheli

引用次数: 14

Exploiting Bus Communication to Improve Cache Attacks on Systems-on-Chips 利用总线通信改进片上系统的缓存攻击

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-01 DOI: 10.1109/ISVLSI.2017.57

Martha Johanna Sepúlveda, Mathieu Gross, A. Zankl, G. Sigl

{"title":"Exploiting Bus Communication to Improve Cache Attacks on Systems-on-Chips","authors":"Martha Johanna Sepúlveda, Mathieu Gross, A. Zankl, G. Sigl","doi":"10.1109/ISVLSI.2017.57","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.57","url":null,"abstract":"Systems-on-Chips (SoCs) are one of the key enabling technologies for the Internet-of-Things (IoT). Given the continuous distribution of IoT devices, data confidentiality and user privacy are of utmost importance. However, with the growing complexity of SoCs, the risk of malware infections and trojans introduced at design time increases significantly. A vital threat to system security are so-called side-channel attacks based on cache observations. While mainly studied on desktop and server systems, recent publications have analyzed cache attacks on mobile devices and network-on-chip platforms. In this work, we investigate cache attacks on System-on-Chips implementing bus based communication. To this end, we present two contributions. First, we demonstrate an improved Prime+Probe based cache attack on AES-128 that, for the first time, exploits the bus communication to increase its efficiency. Second, we integrate two countermeasures (Shuffling and Mini-table) and evaluate their impact on the attack. The results show that our improved attack recovers the full key twice as fast as Prime+Probe without exploiting bus communication. Moreover, we propose protection techniques that are feasible and effectively mitigate both original and improved attack.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"1042 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131624952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

PACT: Priority-Aware Phase-Based Cache Tuning for Embedded Systems 基于优先级感知的基于阶段的嵌入式系统缓存调优

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-01 DOI: 10.1109/ISVLSI.2017.77

Sam Gianelli, Tosiron Adegbija

引用次数: 2

A Workload Characterization for the Internet of Medical Things (IoMT) 医疗物联网(IoMT)的工作量表征

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-01 DOI: 10.1109/ISVLSI.2017.60

Ankur Limaye, Tosiron Adegbija

引用次数: 17

A Flexible Pay-per-Device Licensing Scheme for FPGA IP Cores FPGA IP核的灵活的按设备付费许可方案

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-01 DOI: 10.1109/ISVLSI.2017.123

K. S. Kumar, S. Sahoo, Abhishek Mahapatra, Ayass Kant Swain, K. Mahapatra

引用次数: 10

Adiabatic Computing Based Low-Power and DPA-Resistant Lightweight Cryptography for IoT Devices 基于绝热计算的物联网设备低功耗和抗dpa轻量级加密技术

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-01 DOI: 10.1109/ISVLSI.2017.115

H. Thapliyal, T. S. S. Varun, S. D. Kumar

{"title":"Adiabatic Computing Based Low-Power and DPA-Resistant Lightweight Cryptography for IoT Devices","authors":"H. Thapliyal, T. S. S. Varun, S. D. Kumar","doi":"10.1109/ISVLSI.2017.115","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.115","url":null,"abstract":"Internet of Things (IoT) devices are mostly small and operate wirelessly on limited battery supply, and therefore have stringent constraints on power consumption and hardware resources. Lightweight cryptography (LWC) provides cryptographic solutions for resource-constrained IoT devices. LWC based IoT devices are vulnerable to side-channel attacks such as Differential Power Analysis (DPA). The existing CMOS-based countermeasures for DPA are not suitable for circuits working under energy constraints. Adiabatic logic is one of the promising computing paradigms to design energy-efficient and DPAresistant hardware. Therefore, we have investigated the usefulness of adiabatic logic for low-power and DPA-resistant LWC for IoT devices. In this paper, the PRESENT-80 LWC algorithm is used as a benchmark circuit. The PRESENT-80 algorithm is implemented using Symmetric Pass Gate Adiabatic Logic (SPGAL). SPICE simulations at 12.5 MHz validated that one round of PRESENT-80 implemented using SPGAL gates saves 83% and 91% of power consumption in comparison to CMOS and SABL (Sense Amplifier Based Logic) based implementations, respectively. The security of SPGAL based PRESENT-80 has been evaluated by performing a DPA attack through SPICE simulations. We proved that the SPGAL-based implementation of the PRESENT-80 algorithm is resistant to DPA attacks. Further, low-leakage nano-electronic device FinFET can provide powerefficient solutions for IoT devices. Therefore, the design of the PRESENT-80 algorithm using FinFET based SPGAL gates is also presented. The simulations proved that adiabatic FinFET circuits consume low-power and are more resistant to DPA attacks as compared to adiabatic CMOS circuits.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134195801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

A Hierarchical and Programmable OTA-C Filter 一种分层可编程OTA-C滤波器

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-01 DOI: 10.1109/ISVLSI.2017.95

M. Bhanja, B. Ray

引用次数: 4

Analysis of Side-Channel Attack AES Hardware Trojan Benchmarks against Countermeasures 侧信道攻击AES硬件木马基准测试对策分析

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2017-07-01 DOI: 10.1109/ISVLSI.2017.106

K. SudeendraKumar, S. Sahoo, Abhishek Mahapatra, Ayass Kant Swain, K. Mahapatra

{"title":"Analysis of Side-Channel Attack AES Hardware Trojan Benchmarks against Countermeasures","authors":"K. SudeendraKumar, S. Sahoo, Abhishek Mahapatra, Ayass Kant Swain, K. Mahapatra","doi":"10.1109/ISVLSI.2017.106","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.106","url":null,"abstract":"Hardware Trojan (HT) is one of the well known hardware security issue in research community in last one decade. HT research is mainly focused on HT detection, HT defense and designing novel HT's. HT's are inserted by an adversary for leaking secret data, denial of service attacks etc. Trojan benchmark circuits for processors, cryptography and communication protocols from Trust-hub are widely used in HT research. And power analysis based side channel attacks and designing countermeasures against side channel attacks is a well established research area. Trust-Hub provides a power based side-channel attack promoting Advanced Encryption Standard (AES) HT benchmarks for research. In this work, we analyze the strength of AES HT benchmarks in the presence well known side-channel attack countermeasures. Masking, Random delay insertion and tweaking the operating frequency of clock used in sensitive operations are applied on AES benchmarks. Simulation and power profiling studies confirm that side-channel promoting HT benchmarks are resilient against these selected countermeasures and even in the presence of these countermeasures; an adversary can get the sensitive data by triggering the HT.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134020274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6