Resilient Cell-Based Architecture for Time-to-Digital Converter

Abstract

This paper proposes a resilient Time-to-Digital Converter (TDC) that lends itself to cell-based design automation. We adopt a shrinking-based architecture with a number of distinctive techniques. First of all, a specialized on-chip re-calibration scheme is developed so that the real-time transfer function of the TDC in silicon (which maps an input pulse-width to its corresponding output code) can be derived on the chip and thereby the absolute value (instead of just a relative code) of an input pulse-width under measurement can be reported. Secondly, the sampling errors stemming from the jitters of training clocks used in the calibration scheme are mitigated by the principle of multi sampling. Thirdly, a flexible coarse-shrinking block is adopted and an automatic adjustment scheme is employed so that the coarse-shrinking block can adjust itself when operated under different input pulse-width ranges.