High Speed Power Efficient Carry Select Adder Design

Abstract

Adders are basic building blocks of any processor or data path application. For the design of high performance processing units high speed adders with low power consumption is a requirement. Carry Select Adder (CSA) is known to be one of the fastest adders used in many data processing applications. In this paper, we present a new CSA architecture using Manchester carry chain(MCC) in multioutput domino CMOS logic. It employs a novel MCC blocks in an hierarchical approach in the design of the CSA. The proposed design is validated by implementation of 16 and 32-bit adder circuits in a standard 45nm CMOS process technology. This proposed work evaluates the performance of the proposed designs in terms of delay, power consumption and hardware overhead. The results are analyzed and compared with existing fast adder architectures to prove its efficiency. The simulation results shows that the proposed architecture achieves two fold advantages in terms of power-delay product (PDP) and hardware overhead.