2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)最新文献_第5页

Switched Capacitors Charge Pump with half-floating Topology for a high-efficient Solar Energy Harvester 一种用于高效太阳能收集器的半浮动拓扑开关电容器充电泵

2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268631

Alberto Lopez-Gasso, A. Beriain, H. Solar, R. Berenguer

引用次数: 1

DCIS 2020 List Reviewer Page DCIS 2020名单审稿人页面

2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2020-11-18 DOI: 10.1109/dcis51330.2020.9268663

引用次数: 0

A physically based SPICE model for RRAMs including RTN 基于物理的 RRAM（包括 RTN）SPICE 模型

2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268665

G. González-Cordero, M. B. González, F. Campabadal, F. Jiménez-Molinos, J. Roldán

引用次数: 4

Evaluation of Software Inter-Processor Synchronization Methods for the Zynq-UltraScale+ Architecture Zynq-UltraScale+架构的软件处理器间同步方法评估

2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268616

Rubén Nieto, E. Díaz, R. Mateos, Álvaro Hernández

{"title":"Evaluation of Software Inter-Processor Synchronization Methods for the Zynq-UltraScale+ Architecture","authors":"Rubén Nieto, E. Díaz, R. Mateos, Álvaro Hernández","doi":"10.1109/DCIS51330.2020.9268616","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268616","url":null,"abstract":"Current embedded systems provide diverse functionalities and their features are evolving constantly. This is the case of the Zynq-UltraScale+ (US+) MPSoC family, where it is possible to find a System-on-Chip (SoC) architecture with an Application Processor Unit (APU) containing up to four Cortex A53 processing units, as well as Graphics Processor Units (GPUs) or Real-Time Processor Units (RPUs) in the same device. Nevertheless, the synchronization among these different units is crucial whether tackling a multi-core approach, especially in applications in standalone mode, without an Operating System (OS). In this work, two methods of synchronization among the four cores of the APU in a Zynq-US+ MPSoC device are presented. One of them is based on sending interrupts using the InterProcessor Interrupt (IPI), whereas the other is based on the use of atomic instructions and mutual exclusion variables (mutex). Both methods are managed by the exchange of messages between the processors, previously defined by and for the application. The experimental results presented here allow both proposals to be compared in terms of running times, also considering the particular cases of either a cascaded synchronization among the different cores or a broadcast synchronization among processors.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130528054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reduction of Parity Overhead in a Subset of Orthogonal Latin Square Codes 正交拉丁方码子集中奇偶开销的降低

2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268637

P. Reviriego, Shanshan Liu, A. Sánchez-Macián, Liyi Xiao, J. A. Maestro

引用次数: 1

Evaluation of a Reduced Precision Redundancy FFT Design 低精度冗余FFT设计的评价

2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268634

L. A. García-Astudillo, A. Lindoso, M. Portela, L. Entrena

引用次数: 1

Can Hyperspectral Images be used to detect Brain tumor pixels and their malignant phenotypes? 高光谱图像可以用来检测脑肿瘤像素及其恶性表型吗?

2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268641

A. Martínez-González, A. D. Valle, H. Fabelo, S. Ortega, G. Callicó

{"title":"Can Hyperspectral Images be used to detect Brain tumor pixels and their malignant phenotypes?","authors":"A. Martínez-González, A. D. Valle, H. Fabelo, S. Ortega, G. Callicó","doi":"10.1109/DCIS51330.2020.9268641","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268641","url":null,"abstract":"Neurosurgeons encounter a number of difficulties during brain tumor resection, even when using advanced imaging techniques. The most important are: excessive extraction of normal (healthy) tissue, and inadvertently leaving small sections of tumor tissue un-resected. This study attempts to help neurosurgeons to accurately determine brain tumor boundaries in the resection process using hyperspectral images. We design real-time classification algorithms to determine the type of tissue located at each pixel using technology that could be made accessible to most hospitals. The pixel classifier function is personalized for each of the 13 in-vivo and in-vitro glioblastoma samples by training in situ working with a region of pixels selected for each label. At a certain point during the resection, the surgeon selects a small area of tumor and healthy tissue from the RGB image and our mathematical model provides the classification map for the full image. We also suggest a personalized separator function for each label in order to find cell families with the hyperspectral signature. Mean intra-patient sensitivity was 89% and 85% for in-vivo and in-vitro samples respectively; however, mean specificity was 96% and 92% respectively. Our model allows the spatial detection of different tumor (or healthy) clones that could be related to phenotype heterogeneity within the brain. We find different vasculature and tumor families within patients which might be related to tumor invasion of the vasculature, and different degrees of tumor malignancy, respectively.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121264088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Secure Critical Traffic of the Electric Sector over Time-Sensitive Networking 确保电力部门在时间敏感网络上的关键流量

2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268613

L. Muguira, Jesús Lázaro, Sara Alonso, A. Astarloa, Mikel Rodríguez

{"title":"Secure Critical Traffic of the Electric Sector over Time-Sensitive Networking","authors":"L. Muguira, Jesús Lázaro, Sara Alonso, A. Astarloa, Mikel Rodríguez","doi":"10.1109/DCIS51330.2020.9268613","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268613","url":null,"abstract":"The convergence of operational technology (OT) and information technology (IT) in the same network is essential for upcoming digitized scenarios, such as the Electric Sector, Smart-Grid, and Substation Automation Systems (SAS). The typical separation of these two areas in the traditional Ethernet standard is increasingly disappearing. Furthermore, security requirements must be fulfilled in the involved systems and infrastructures. It is the case of the Electric Sector, which is aware of this necessity and it is trying to protect all digitized data streams, even the most critical one with tight real-time requirements. The technology that allows this OT/IT integration is Deterministic Ethernet. The standard and interoperable Deterministic Ethernet alternative is named Time-Sensitive Networking (TSN) standard. TSN offers a convergent, interoperable, deterministic, and uniform network. However, it lacks from security mechanisms for real-time traffic. This paper presents a concept-proof work used to prove that the hard real-time traffic used in the power substations can be protected using wire-speed cryptography and data-flow hardware processing approach.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121651382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A Memristor-based Quaternary Memory with Adaptive Noise Tolerance 基于忆阻器的自适应噪声容限四元存储器

2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268675

Arezoo Dabaghi Zarandi, A. Rubio, M. R. Reshadinezhad

引用次数: 0

FPGA Implementation of Random Vector Functional Link Networks based on Elementary Cellular Automata 基于初等元胞自动机的随机向量功能链路网络的FPGA实现

2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268673

Alejandro Morán, V. Canals, M. Roca, E. Isern, J. Rosselló

{"title":"FPGA Implementation of Random Vector Functional Link Networks based on Elementary Cellular Automata","authors":"Alejandro Morán, V. Canals, M. Roca, E. Isern, J. Rosselló","doi":"10.1109/DCIS51330.2020.9268673","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268673","url":null,"abstract":"Today, there is an increasing demand in designing and deploying low-power Machine Learning (ML) models for edge applications such as mobile phones or specific purpose smart cameras and voice processing systems. These products might incorporate low power processors and ASICs to manage communications and meet power/energy consumption specifications in computationally intensive tasks. These ML tasks usually include Deep Learning systems that require a considerably number of multiply-accumulate (MAC) operations, thus impacting in both hardware and energy requirements. Here we show a novel ML hardware design optimized for edge applications that considerably reduces the number of MAC operations based on incorporating Elementary Cellular Automata within a Random Vector Functional Link Network architecture. As a proof of concept, the proposed system is implemented in a Field-Programmable Gate Array and applied to the well known MNIST dataset, showing high-performance characteristics along with a considerably higher energy efficiency if compared with recently published ML-hardware designs.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126364398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0