2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)最新文献_第4页

DCIS 2020 Index DCIS 2020指数

2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2020-11-18 DOI: 10.1109/dcis51330.2020.9268651

引用次数: 0

Autonomous self-powered potentiostat architecture for biomedical wearable applications. 用于生物医学可穿戴应用的自主自供电电位器架构。

2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268667

Javier Aguilar, Albert Álvarez-Carulla, Valeria Colmena, Oscar Carreras, Genis Rabost, M. Puig-Vidal, J. Colomer-Farrarons, Xavier Muñoz, P. Miribel-Català, J. Punter-Villagrasa

引用次数: 2

Analysing the interference of Xen hypervisor in the network speed 分析Xen hypervisor对网络速度的干扰

2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268648

Sara Alonso, Jesús Lázaro, J. Jiménez, L. Muguira, Alejandro Largacha

{"title":"Analysing the interference of Xen hypervisor in the network speed","authors":"Sara Alonso, Jesús Lázaro, J. Jiménez, L. Muguira, Alejandro Largacha","doi":"10.1109/DCIS51330.2020.9268648","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268648","url":null,"abstract":"The use of hypervisors is constantly growing on account of their benefits. For some applications with hard realtime constraints, it is interesting to analyze the speed reduction that could cause. MPSoC boards are suitable for the use of hypervisors thanks to having an FPGA which allows the user to design the hardware and Cortex A53 cores, with armv8 architecture, which have virtualization extensions. The board has been validated with Xen hypervisor. This paper compares five scenarios to characterize the impact of the hypervisor layer on the speed of a network connection: a standalone application, Petalinux directly running on hardware, Petalinux running in Xen Dom0, Petalinux running in Xen DomU paravirtualizing the network and a Petalinux running in Xen DomU pass-throughing the network. It also characterizes the delay of the network connection in some scenarios as a complementary measurement. All the cases are implemented in the Zynq ZCU102 board. It is shown that a Xen hypervisor layer creates a considerable reduction in network speed. Provided that the network is settled down in passthrough mode, the network speed in DomU is almost the same as if there was no hypervisor.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117071503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

FrailWear: A Wearable IoT Device for Daily Activity Monitoring of Elderly Patients frrailwear:一种用于老年患者日常活动监测的可穿戴物联网设备

2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268629

Sergio Lluva Plaza, J. M. V. Carrizo, Juan Jesús García Domínguez, Ana Jiménez Martín, David Gualda Gómez

引用次数: 2

Hyperspectral Images Acquisition: an Efficient Capture and Processing Stitching Procedure for Medical Environments 高光谱图像采集:用于医疗环境的高效捕获和处理拼接程序

2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268658

Gonzalo Rosa, Marta Villanueva, Jaime Sancho, Gemma Urbanos, Luisa Ruiz, M. Villa, Alberto Martín, E. Juárez, Luis Jiménez, M. Chavarrías, Alfonso Lagares, C. Sanz

引用次数: 1

RISC-V processors design: a methodology for cores development RISC-V处理器设计:一种核心开发方法

2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268639

A. Barriga

引用次数: 0

A Hardware-Accelerated Qubit Control System for Quantum Information Processing 量子信息处理的硬件加速量子比特控制系统

2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268643

N. Messaoudi, C. Crocker, M. Almendros

{"title":"A Hardware-Accelerated Qubit Control System for Quantum Information Processing","authors":"N. Messaoudi, C. Crocker, M. Almendros","doi":"10.1109/DCIS51330.2020.9268643","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268643","url":null,"abstract":"In this paper we present a flexible, highperformance, integrated qubit control system using modular PXIe equipment. To manipulate qubits, a classical control system is required to generate and acquire a mix of baseband, radio frequency, and/or optical signals, with the specific mix different for each qubit technology. Typically, a quantum system requires many of these signals with a high degree of synchronization and phase coherence, and increasingly needs real-time data processing and on-the-fly sequencing capabilities for feedback experiments. The proposed system is scalable to hundreds of channels, all of them being phase coherent and fully time-synchronized.The system includes a programmable real-time sequencer for precise execution timing and decision making; and open FPGA capabilities for custom Digital Signal Processing (DSP) by hardware. Using the latter, we present FPGA IP to generate one-/two-qubit gates efficiently with the AWG, and to analyze high-frequency signals to measure the qubit states in real time on the digitizers. This IP features very low latencies for Quantum Error Correction (QEC) and Frequency Division Multiplexing (FDM) capabilities, among others.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114970786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Design and Characterization of Non-planar 3D-printed Passive UHF-RFID Tag 非平面3d打印无源超高频rfid标签的设计与表征

2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268666

N. Vidal, Arnau Salas Barenys, Aleix Garcia, J. Romeu, Giselle González, L. Jofre, J. López-Villegas

引用次数: 0

Selection of SRAM Cells to improve Reliable PUF implementation using Cell Mismatch Metric 使用单元失配度量来选择SRAM单元以提高可靠的PUF实现

2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268669

A. Alheyasat, G. Torrens, S. Bota, B. Alorda

{"title":"Selection of SRAM Cells to improve Reliable PUF implementation using Cell Mismatch Metric","authors":"A. Alheyasat, G. Torrens, S. Bota, B. Alorda","doi":"10.1109/DCIS51330.2020.9268669","DOIUrl":"https://doi.org/10.1109/DCIS51330.2020.9268669","url":null,"abstract":"Physically Unclonable Functions (PUFs) are low-cost cryptographic primitives implemented in secret key generation and device authentication strategies. SRAM-PUFs are widely well-known as entropy source; however, they mainly experience a low reproducibility of the challenge-response pair because of non-deterministic noise conditions during the process of power-up. The reliability of SRAM-PUFs achieved these days comes by using complex error correcting codes (ECCs) combined with Fuzzy extractor structures introducing an increment in terms of power consumption, area cost and complexity of the design. In this paper we define an effective metric to classify the SRAM cells identifying the most reliable cells generating high reproductible responses for the PUF implementation and, identifying the most unpredictable ones for Random Number Generator (RNG). This metric is obtained from the mismatch between the cell’s inverters and the start-up behavior. Also, the noise in the PUF is modeled to validate the classification results obtained by the proposed metric. The proposed metric can be used during SRAM PUF design to explore the impact on reliable cells significantly increasing the reproducibility of the PUF and minimizing the dependability on ECCs and Fuzzy extractor.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"49 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120885619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

DAC mismatch shaping in Discrete Time Sigma Delta ADCs with non uniform quantizer 带非均匀量化器的离散时间σ δ adc的DAC失配整形

2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2020-11-18 DOI: 10.1109/DCIS51330.2020.9268615

Pablo Vera, S. Patón

引用次数: 0