Evaluation of a Reduced Precision Redundancy FFT Design

Abstract

Fault-tolerant designs for space applications on SRAM-based FPGAs typically require Distributed Triple Modular Redundancy (DTMR) or Block Triple Modular Redundancy (BTMR) to mitigate faults induced by ionizing radiation. These methods lead to a large area overhead, which, in turn, can make the design more susceptible to the radiation effects. The Reduced Precision Redundancy (RPR) technique has been proposed as a trade-off between area overhead and reliability. In this work, the RPR hardening technique is reviewed and compared to TMR by performing fault injection campaigns using a hardened Fast Fourier Transform (FFT) block as a case study. Results show that the implemented RPR not only saves FPGA resources, but also reduces the critical error rate and the impact of Common Mode Failures (CMF) with respect to the TMR solution.