Alberto Lopez-Gasso, A. Beriain, H. Solar, R. Berenguer
{"title":"Switched Capacitors Charge Pump with half-floating Topology for a high-efficient Solar Energy Harvester","authors":"Alberto Lopez-Gasso, A. Beriain, H. Solar, R. Berenguer","doi":"10.1109/DCIS51330.2020.9268631","DOIUrl":null,"url":null,"abstract":"This paper describes the design of a fully-integrated high-efficiency power management unit of a solar energy harvester for smart nodes of Internet of Things (IoT) networks. The proposed topology presents a half-floating input to avoid losses charging the top/button plate of the stray capacitors in each clock cycle. Moreover, the proposed harvester is fully integrated on-chip without the need of external components and occupying an area of 0.69 mm2. Simulation results show efficiencies above 80% in the range of 5-25μW output power connected to a 1.42 cm2 solar cell with indoor light conditions (500-1000 lux).","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"PP 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DCIS51330.2020.9268631","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper describes the design of a fully-integrated high-efficiency power management unit of a solar energy harvester for smart nodes of Internet of Things (IoT) networks. The proposed topology presents a half-floating input to avoid losses charging the top/button plate of the stray capacitors in each clock cycle. Moreover, the proposed harvester is fully integrated on-chip without the need of external components and occupying an area of 0.69 mm2. Simulation results show efficiencies above 80% in the range of 5-25μW output power connected to a 1.42 cm2 solar cell with indoor light conditions (500-1000 lux).