2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)最新文献_第2页

Key Circuit Building Blocks for 5G Millimeter-Wave Phased-Array Transceiver Front-End (Invited) 5G毫米波相控阵收发前端关键电路构建模块(特邀)

2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2018-11-01 DOI: 10.1109/CICTA.2018.8705946

Dixian Zhao, Peng Gu, Yongran Yi, Chongyu Yu

引用次数: 0

A 2.5D integrated L band Receiver based on High resistivity Si interposer 基于高阻硅中间体的2.5D集成L波段接收机

2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2018-11-01 DOI: 10.1109/CICTA.2018.8705960

Shengli Ma, Y. Chai, Jun Yan, Han Cai, Liu-lin Hu, Shuwei He, Wei Wang, Jing Chen, Yufeng Jin

{"title":"A 2.5D integrated L band Receiver based on High resistivity Si interposer","authors":"Shengli Ma, Y. Chai, Jun Yan, Han Cai, Liu-lin Hu, Shuwei He, Wei Wang, Jing Chen, Yufeng Jin","doi":"10.1109/CICTA.2018.8705960","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705960","url":null,"abstract":"Transmitter/Receiver (T/R) is a basic part for the RF front-end module, whose miniaturization and integration are very important for the improvement in integration density, function complexity and performance. The state of art of high performance T/R is mainly realized with heterogeneous integration based on advance ceramics such as High Temperature Co-fired Ceramic (HTCC) and Low Temperature Co-fired Ceramic (LTCC). This scheme is helpful to fully utilize the excellent performance of various devices based on substrate such as GaAs, InP, and GaN substrate, however, it confronts shortcomings in re-wiring lines of low precision, shrinkage mismatch during co-firing process, low thermal conductivity. TSV interposer having its Re-wiring line realized with IC back-end metallization process, MEMS process, etc., and using Through-Silicon-Via (TSV) to achieve vertical interconnections between rewiring lines on both surface, is able to provide a good match in rewiring line with RF microelectronic chips, factoring in improvement in RF loss properties with high-resistivity Si as substrate instead of normal low resistivity Si, therefore is acknowledged to be a competitive package substrate for building a highly integrated RF system. In this context, we present a 2.5D integrated L-band Receiver based on TSV interposer, the test results prove the feasibility of 2.5D RF integration enabled by high-resistivity Si interposer.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134408556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

28-nm Bulk and FDSOI Cryogenic MOSFET : (Invited Paper) 28纳米体积和FDSOI低温MOSFET:(特邀论文)

2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2018-11-01 DOI: 10.1109/CICTA.2018.8706117

A. Beckers, F. Jazaeri, C. Enz

引用次数: 5

Low Temperature Polycrystalline Silicon Thin Film Synaptic Transistor with Bilingual Plasticity for Neuromorphic Computing 具有双语可塑性的低温多晶硅薄膜突触晶体管用于神经形态计算

2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2018-11-01 DOI: 10.1109/CICTA.2018.8706066

Nian Duan, Yi Li, X. Miao, Hsiao-Cheng Chiang, T. Chang

引用次数: 1

The Design Techniques for High-Speed PAM4 Clock and Data Recovery 高速PAM4时钟和数据恢复的设计技术

2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2018-11-01 DOI: 10.1109/CICTA.2018.8706109

Qiwen Liao, Nan Qi, Zhao Zhang, Liyuan Liu, Jian Liu, N. Wu, Xi Xiao, P. Chiang

引用次数: 2

Compact Modeling and Short-Channel Effects of Nanowire MOS Transistors (Invited) 纳米线MOS晶体管的紧凑建模和短沟道效应(特邀)

2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2018-11-01 DOI: 10.1109/CICTA.2018.8705955

H. Wong

{"title":"Compact Modeling and Short-Channel Effects of Nanowire MOS Transistors (Invited)","authors":"H. Wong","doi":"10.1109/CICTA.2018.8705955","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705955","url":null,"abstract":"It is expected that the next device structure evolution will be the Silicon-on-Nothing (SON) Gate-All-Around (GAA) nanowire structure. In principle, the nanowire transistor should have even better scalability than the FinFET used in the state-of-the-art CMOS technology because of its fewer parasitic components on substrate and better gate electrostatics control as gate area is extended from three sides to the whole circumference. In addition, ballistic charge transport may also be possible with the ultra-short gate length. This work reports the attempt of modeling silicon GAA nanowire transistors by considering the ballistic transport and with some effective measures for accounting the subband energy level quantization under some specific surface potential profiles approximations. Good agreements with the simulation results were obtained. In particular, for the subthreshold characteristics obtained from the model, it indicates that short-channel effects will become significant again in the nanowire transistor because of the source subband energy reduction induced by the drain bias. Considering the limit of nanowire size scaling which made length-to-radius ratio not to be larger enough and the non-ideal effects such as surface scattering and gate leakage, it seems that the benefits of replacing FinFET with nanowire GAA transistor may not be that large and there is no much more generations for further scaling.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116933005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

ICTA 2018 Author Index ICTA 2018作者索引

2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2018-11-01 DOI: 10.1109/cicta.2018.8705953

引用次数: 0

A 5 ∼14GHz Wideband LNA using 0.13μm SiGe BiCMOS Technology 采用0.13μm SiGe BiCMOS技术的5 ~ 14GHz宽带LNA

2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2018-11-01 DOI: 10.1109/CICTA.2018.8705956

Weipeng He, Zhiqun Li, Yan Yao, Yongbin Xue, Lei Luo, Guoxiao Cheng

引用次数: 0

Design of 140-GHz Frequency Single-Ended and Push-Push Doublers with 31.61dB and 91.19dB Fundamental Suppression 具有31.61dB和91.19dB基波抑制的140 ghz频率单端和推推式倍频器的设计

2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2018-11-01 DOI: 10.1109/CICTA.2018.8705709

Xiaofei Liao, Dixian Zhao

引用次数: 0

An Agile Automatic Frequency Calibration Technique for PLL 一种灵活的锁相环自动频率校准技术

2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2018-11-01 DOI: 10.1109/CICTA.2018.8706068

Xin Ding, Jianhui Wu, Chao Chen

引用次数: 0