Compact Modeling and Short-Channel Effects of Nanowire MOS Transistors (Invited)

Abstract

It is expected that the next device structure evolution will be the Silicon-on-Nothing (SON) Gate-All-Around (GAA) nanowire structure. In principle, the nanowire transistor should have even better scalability than the FinFET used in the state-of-the-art CMOS technology because of its fewer parasitic components on substrate and better gate electrostatics control as gate area is extended from three sides to the whole circumference. In addition, ballistic charge transport may also be possible with the ultra-short gate length. This work reports the attempt of modeling silicon GAA nanowire transistors by considering the ballistic transport and with some effective measures for accounting the subband energy level quantization under some specific surface potential profiles approximations. Good agreements with the simulation results were obtained. In particular, for the subthreshold characteristics obtained from the model, it indicates that short-channel effects will become significant again in the nanowire transistor because of the source subband energy reduction induced by the drain bias. Considering the limit of nanowire size scaling which made length-to-radius ratio not to be larger enough and the non-ideal effects such as surface scattering and gate leakage, it seems that the benefits of replacing FinFET with nanowire GAA transistor may not be that large and there is no much more generations for further scaling.