高速PAM4时钟和数据恢复的设计技术

2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2018-11-01 DOI:10.1109/CICTA.2018.8706109

Qiwen Liao, Nan Qi, Zhao Zhang, Liyuan Liu, Jian Liu, N. Wu, Xi Xiao, P. Chiang

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引用次数: 2

摘要

提出了PAM4格式高速通信中时钟和数据恢复(CDR)的关键技术，包括有效电压电平转换选择、采样位置优化和阈值调整。在此基础上，设计并制作了两个50Gbps的PAM4 CDR，分别为65nm和40nm。测量结果显示，65nm PAM4 CDR的误码率为3.4\times10^{-9}$， 40nm PAM4 CDR的误码率为8\times10^{-9}$。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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The Design Techniques for High-Speed PAM4 Clock and Data Recovery

In this paper, some key techniques of clock and data recovery (CDR) are proposed for PAM4 format high-speed communication, including effective voltage level transitions selection, sampling location optimization and threshold adjustment. Based on these techniques, two 50Gbps PAM4 CDR were designed and fabricated in 65nm and 40nm, respectively. The measurement results show $3.4\times10^{-9}$ BER of 65nm PAM4 CDR and $8\times10^{-9}$ BER of 40nm PAM4 CDR.

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来源期刊

2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)

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