The Design Techniques for High-Speed PAM4 Clock and Data Recovery

Abstract

In this paper, some key techniques of clock and data recovery (CDR) are proposed for PAM4 format high-speed communication, including effective voltage level transitions selection, sampling location optimization and threshold adjustment. Based on these techniques, two 50Gbps PAM4 CDR were designed and fabricated in 65nm and 40nm, respectively. The measurement results show $3.4\times10^{-9}$ BER of 65nm PAM4 CDR and $8\times10^{-9}$ BER of 40nm PAM4 CDR.