M. Karnett, S. Qian, R. Solis, X. Tao, A. Black, S. Boonsanguan, A. Liu
{"title":"The influence of processing conditions on data retention behavior in a deep submicron NVM process","authors":"M. Karnett, S. Qian, R. Solis, X. Tao, A. Black, S. Boonsanguan, A. Liu","doi":"10.1109/ASMC.2003.1194479","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194479","url":null,"abstract":"Detailed investigations and process characterizations were performed to identify and resolve the source for programmed cell charge loss and data retention capability within the EPROM cells of our 0.35 /spl mu/m Non-Volatile Memory (NVM) process technology. Both front- and back-end processing steps influenced the data retention behavior, with the most significant impact arising from the use of a high density plasma (HDP) oxide as the inter-metal dielectric. We postulate that cumulative charge buildup during processing lead to the severe charge retention effects observed and near zero yield at wafer probe.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"2017 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127543547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Cycle time reduction at a major Texas Instruments wafer fab","authors":"K. Potti, M. Whitaker","doi":"10.1109/ASMC.2003.1194477","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194477","url":null,"abstract":"This paper highlights the strategic and tactical applications of simulation modeling and how it was used to reduce cycle time at a major Texas Instruments wafer fab.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128642401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The effectiveness and practical application of human resource development (HRD) programs in the semiconductor industry - a case study of SilTerra Malaysia Sdn Bhd","authors":"A. Lin, R. A. Razak","doi":"10.1109/ASMC.2003.1194490","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194490","url":null,"abstract":"In a workplace where employees are constantly impacted by the environment of change, corporate leaders are faced with critical decisions among myriad choices about how to plan for and affect the evolving lifelong learning needs of their organizations. The challenge for Silterra Malaysia Sdn Bhd (Silterra) and it employees is to identify those needs, implement and execute them. As one of the pioneers in semiconductor fabrication industry in Malaysia, it is the intent of Silterra to create a legacy in the area of training and development. It is the goal of the company to become a learning organization. Continuous learning is a key success of a learning organization. To sustain as a learning organization, the HRD programs are used to develop competency sets for Silterra employees. The evaluation system developed by Donald Kirkpatrick (1979) has been used to measure the effectiveness of HRD programs. However, there is an on-going debate in the field of evaluation about which is the best approach to facilitate the processes involved. This paper reviews current approaches to evaluation of training both in theory and practice applicable to Silterra.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131359090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Characterisation of silicon oxynitrides and high-k dielectric materials by angle-resolved X-ray photoelectron spectroscopy","authors":"P. Mack, R. White, J. Wolstenholme, A. Wright","doi":"10.1109/ASMC.2003.1194486","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194486","url":null,"abstract":"Angle-resolved X-ray photoelectron spectroscopy (ARXPS) has been used to characterise nondestructively silicon oxynitride and high-k film samples. Film thickness values and concentration profiles were determined in each case. Different chemical states of nitrogen were identified in the silicon oxynitride sample and concentration profiles and dose values for each nitrogen state were calculated. ARXPS was also used to study the difference between hafnium oxide films deposited on thermally grown silicon oxide and on HF-etched silicon. The thickness and chemistry of the interfacial layers were characterised.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133042734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Pupilgram imperfections and their effect on lithography","authors":"S. Renwick, S. Slonaker","doi":"10.1109/ASMC.2003.1194468","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194468","url":null,"abstract":"Over the past three years or so, as lens manufacturing has improved and lens aberrations have been continuously reduced, the effects of imperfections in the pupil fill, or the partial-coherence pattern produced by the illuminator of a lithographic tool, are rising up out of the noise level and becoming important. Tools for quantitatively measuring illuminator pupil fill are now becoming increasingly widespread, and the user community is collecting data and asking lithographic tool suppliers what the data mean. Previously, we measured imperfections in the pupil fill of Nikon S204-generation scanners by generating pupilgrams, analyzed them in a manner so as to extract their underlying structure, and compared the results to scaling laws derived from lithographic calculations run with Prolith. At that time, we found that the imperfections seen in that generation of lithographic tools were small enough to have only a minimal effect on litho performance. Now, pupil-fill effects in new-generation high-NA scanners have been measured and characterized. We present a systematic study of pupilgrams, measured with a pinhole reticle while exercising illuminator adjustments, and correlate them with simultaneous measurements of CD uniformity and V-H bias to evaluate the importance of the illuminator in overall CD performance. We have also developed a more sophisticated analysis method to predict the effects of the pupilgrams on litho performance, and we present the correlation between experiment and theory. This work should allow both lithographic tool suppliers and end users to inspect a pupilgram and determine whether it will adversely impact their lithography.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123896217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Evaluation of final test process in 64-Mbit DRAM manufacturing system through simulation analysis","authors":"K. Nakamae, H. Ikeda, H. Fujioka","doi":"10.1109/ASMC.2003.1194493","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194493","url":null,"abstract":"We have evaluated the final test process in a 64-Mbit DRAM manufacturing system through an event-driven simulation analysis concerning the number of chips simultaneously tested by a memory test system. Four test flows for DRAMS and SDRAMs are considered. The overall number of planned production chips during a month is 3 million. The number of chips simultaneously tested is 32, 64, 128, and 256. Simulations for six months were carried out as a function of number of memory test systems by using parameter values extracted from a real final test facility in Japan. From the overall assessments as to the average TAT and the cost per chip, the final test facility should have 14 memory test systems for this production plan where 128 chips are simultaneously tested.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131485693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Tran-Quinn, N. Bell, R. Cook, M. Fung, J. W. Andrews, D. Hilscher, D. Szmyd, V. Saikuma, R. Ketcheson, P. Kellawon, S. Calvelli
{"title":"NPN yield improvement with ozone surface treatment prior to emitter poly deposition","authors":"T. Tran-Quinn, N. Bell, R. Cook, M. Fung, J. W. Andrews, D. Hilscher, D. Szmyd, V. Saikuma, R. Ketcheson, P. Kellawon, S. Calvelli","doi":"10.1109/ASMC.2003.1194509","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194509","url":null,"abstract":"A localized product yield degradation was observed on 0.25um BiCMOS product and was found to correlate to suppression of the NPN base and emitter currents. The addition of an ozone plasma clean prior to emitter polysilicon deposition helped to improve base current distribution across the wafers.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129067803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A dynamic system regulation measure for increasing effective capacity: the X-factor theory","authors":"D. Delp, J. Si, Y. Hwang, B. Pei","doi":"10.1109/ASMC.2003.1194473","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194473","url":null,"abstract":"Due to the complex nature of semiconductor manufacturing it is evident that a single scheduling or regulation technique cannot best optimize the system dynamics for reducing cycle time and increasing throughput. The throughput of the system can increase to the effective capacity level of the system. When the throughput of the system approaches the effective capacity the product cycle time can dramatically increase. The \"knee\" of the performance curve indicates an operating point for fabs to maximize throughput while keeping the product cycle time relatively low. By increasing the effective capacity, i.e. adding a machine or improving a process, the product cycle time can be lowered or the system throughput increased by producing a shift in the \"knee\" of the performance curve. The bottleneck, typically defined as the most heavily utilized machine group, is often the target for increasing the system effective capacity. We will analyze the bottleneck along with other system capacity regulation measures to systematically study the relationship between bottleneck, X-factor, cycle time, and throughput measurements.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"6 22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123741877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Extending the HDP-CVD technology to the 90 nm node and beyond with an in-situ etch assisted (ISEA) HDP-CVD process","authors":"J. Radecker, H. Weber","doi":"10.1109/ASMC.2003.1194480","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194480","url":null,"abstract":"High density plasma chemical vapor deposition (HDP-CVD) technology is currently not able to provide the semiconductor industry with a void-free fill process for shallow trench isolation (STI) with 100 nm gap width and aspect ratios (AR) higher than 4:1. For the first time a method is shown, which can extend the well-known HDP-CVD technology to provide void-free gap fill to gap widths below 90 nm and AR higher than 6:1. Key to this is the addition of nitrogen trifluoride (NF/sub 3/) to the conventional silane/oxygen HDP-CVD chemistry. As a result of this component, an in-situ fluorine based isotropical oxide etch, gap fill capability will be improved. Compared to other fill alternatives a very good oxide quality is obtained for this process. The incorporated F and N show only a minor impact on film quality. The integration scheme does not need to be changed. Results from fully integrated DRAM wafers showed comparable yield to conventional HDP split groups with no additional reliability risk.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127241694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Integrated web-based architecture for correlative engineering data analysis and decision support","authors":"N. Tandon, D. Cleverdon, B. Hinshaw","doi":"10.1109/ASMC.2003.1194506","DOIUrl":"https://doi.org/10.1109/ASMC.2003.1194506","url":null,"abstract":"In the dynamic environment of frequently changing technology cycles, semiconductor manufacturing companies strive to optimize processes quickly to increase yields across a myriad of device types being designed and processed simultaneously in a factory. Immense quantities of process and test data are usually collected during silicon processing, and computerized tools are used to extract and analyze the engineering data for decision support. An integrated web-based architecture using Spotfire DecisionSite/spl trade/ framework has been implemented at Kilby Center (KFAB) of Texas Instruments (TI) for engineering data analysis. Rather than merely providing access to the different data sets to the end users, the established infrastructure provides an enormous value by facilitating data merges and correlative analyses across the multiple and complex data warehouses. Ease of employing these correlation techniques has lead to improvements in device designs, process corrections, equipment maintenance, and yields.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"28 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121889214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}