M. Karnett, S. Qian, R. Solis, X. Tao, A. Black, S. Boonsanguan, A. Liu
{"title":"The influence of processing conditions on data retention behavior in a deep submicron NVM process","authors":"M. Karnett, S. Qian, R. Solis, X. Tao, A. Black, S. Boonsanguan, A. Liu","doi":"10.1109/ASMC.2003.1194479","DOIUrl":null,"url":null,"abstract":"Detailed investigations and process characterizations were performed to identify and resolve the source for programmed cell charge loss and data retention capability within the EPROM cells of our 0.35 /spl mu/m Non-Volatile Memory (NVM) process technology. Both front- and back-end processing steps influenced the data retention behavior, with the most significant impact arising from the use of a high density plasma (HDP) oxide as the inter-metal dielectric. We postulate that cumulative charge buildup during processing lead to the severe charge retention effects observed and near zero yield at wafer probe.","PeriodicalId":178755,"journal":{"name":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","volume":"2017 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASMC.2003.1194479","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Detailed investigations and process characterizations were performed to identify and resolve the source for programmed cell charge loss and data retention capability within the EPROM cells of our 0.35 /spl mu/m Non-Volatile Memory (NVM) process technology. Both front- and back-end processing steps influenced the data retention behavior, with the most significant impact arising from the use of a high density plasma (HDP) oxide as the inter-metal dielectric. We postulate that cumulative charge buildup during processing lead to the severe charge retention effects observed and near zero yield at wafer probe.