2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682)最新文献

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CalmADM/spl trade/: an audio DSP module based on CalmRISC/spl trade/ CalmADM/spl trade/:基于CalmRISC/spl trade/的音频DSP模块
2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 2003-10-14 DOI: 10.1109/SIPS.2003.1235644
Joong-Eon Lee, Yun-Hwan Kim, Kyoung-Mook Lim, J. Park, Seh-Woong Jeong
{"title":"CalmADM/spl trade/: an audio DSP module based on CalmRISC/spl trade/","authors":"Joong-Eon Lee, Yun-Hwan Kim, Kyoung-Mook Lim, J. Park, Seh-Woong Jeong","doi":"10.1109/SIPS.2003.1235644","DOIUrl":"https://doi.org/10.1109/SIPS.2003.1235644","url":null,"abstract":"We introduce CalmADM, an audio DSP module based on CalmRISC. CalmADM is based on Samsung's 16-bit microprocessor, CalmRISC16, and its 24-bit DSP coprocessor, CalmMAC24. Two new architectures are adopted in CalmADM. One is shared data cache. With this new caching scheme, we can reduce on-chip memory area while not losing cache performance and programming flexibility. The other is sequential stream buffer. This small buffer takes full charge of input/output audio stream data. Therefore, data caches in CalmADM do not suffer from performance loss caused by cache misses for input/output stream data. The area of CalmADM is about 290K in gate count including on-chip cache memories. The performance we achieved is 38 MIPS for 5.1-channel Dolby AC3 decoding and 40 MIPS for 7.1-channel MPEG2 audio layer2 decoding, including off-chip memory access overhead.","PeriodicalId":173186,"journal":{"name":"2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116103369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Efficient scalable hardware architecture for Montgomery inverse computation in GF(p) GF(p)中Montgomery逆计算的高效可扩展硬件架构
2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 2003-10-14 DOI: 10.1109/SIPS.2003.1235650
A. Gutub, A. Tenca
{"title":"Efficient scalable hardware architecture for Montgomery inverse computation in GF(p)","authors":"A. Gutub, A. Tenca","doi":"10.1109/SIPS.2003.1235650","DOIUrl":"https://doi.org/10.1109/SIPS.2003.1235650","url":null,"abstract":"The Montgomery inversion is a fundamental computation in several cryptographic applications. We propose a scalable hardware architecture to compute the Montgomery modular inverse in GF(p). We suggest a new correction phase for a previously proposed almost Montgomery inverse algorithm to calculate the inversion in hardware. The intended architecture is scalable, which means that a fixed-area module can handle operands of any size. The word-size, which the module operates, can be selected based on the area and performance requirements. The upper limit on the operand precision is dictated only by the available memory to store the operands and internal results. The scalable module is in principle capable of performing infinite-precision Montgomery inverse computation of an integer, modulo a, prime number. This scalable hardware is compared with a previously proposed fixed (fully parallel) design showing very attractive results.","PeriodicalId":173186,"journal":{"name":"2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122440026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Optimal data transfer and buffering schemes for JPEG2000 encoder JPEG2000编码器的最佳数据传输和缓冲方案
2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 2003-10-14 DOI: 10.1109/SIPS.2003.1235665
M. Chiu, Kun-Bin Lee, C. Jen
{"title":"Optimal data transfer and buffering schemes for JPEG2000 encoder","authors":"M. Chiu, Kun-Bin Lee, C. Jen","doi":"10.1109/SIPS.2003.1235665","DOIUrl":"https://doi.org/10.1109/SIPS.2003.1235665","url":null,"abstract":"The paper presents optimal data transfer and buffering schemes for a JPEG2000 encoder. The data transfer scheme combines bit-level zero run-length coding and addressing mode to reduce data transfer time between discrete wavelet transform (DWT) and embedded block coding with optimized truncation (EBCOT) to 21%. Furthermore, this data transfer scheme also helps in word-to-bitplane data format conversion from DWT to EBCOT. On the other hand, by jointly considering the coding flow of both lifting-based DWT and EBCOT with different design parameters, the reduction in total buffer requirement for both DWT and EBCOT can be up to a factor of 4.22.","PeriodicalId":173186,"journal":{"name":"2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682)","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122844560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
A cost-effective implementation of object-based motion estimation 基于目标的运动估计的经济有效的实现
2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 2003-10-14 DOI: 10.1109/SIPS.2003.1235660
J. C. Greiner, R. Sethuraman, J. van Meerbergen, G. de Haan
{"title":"A cost-effective implementation of object-based motion estimation","authors":"J. C. Greiner, R. Sethuraman, J. van Meerbergen, G. de Haan","doi":"10.1109/SIPS.2003.1235660","DOIUrl":"https://doi.org/10.1109/SIPS.2003.1235660","url":null,"abstract":"Emerging applications in the mobile and automotive industries can benefit from a solution which can segment an image into objects. Although originally not developed for these applications, object-based motion estimation (OME) is an algorithm which provides such a segmentation. We map this algorithm on an application specific instruction processor (ASIP) based on a very long instruction word (VLIW) template. An analysis of the computational requirements is made, using video format conversion as an application, since emerging applications are not available yet. We also propose a multi-level caching architecture to keep bandwidth and power requirements low and discuss algorithmic changes to OME, which are necessary for OME to be mapped on an ASIP VLIW. A quality comparison of the resulting vector fields is made as well.","PeriodicalId":173186,"journal":{"name":"2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128212173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A real time, low latency, hardware implementation of the 2D discrete wavelet transformation for streaming image applications 一个实时,低延迟,硬件实现的二维离散小波变换的流图像应用程序
2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 2003-10-14 DOI: 10.1109/SIPS.2003.1235659
O. Benderli, Y. Tekmen, N. Ismailoglu
{"title":"A real time, low latency, hardware implementation of the 2D discrete wavelet transformation for streaming image applications","authors":"O. Benderli, Y. Tekmen, N. Ismailoglu","doi":"10.1109/SIPS.2003.1235659","DOIUrl":"https://doi.org/10.1109/SIPS.2003.1235659","url":null,"abstract":"We present a 2D discrete wavelet transformation (DWT) hardware for applications where row-based raw image data is streamed in at high bandwidths and local buffering of the entire image is not feasible. The latency that is introduced as the images stream through the DWT filter and the amount of locally stored image data is a function of the image and tile size. For an n/sub 1//spl times/n/sub 2/ size image processed using (n/sub 1//k/sub 1/)/spl times/(n/sub 2//k/sub 2/) sized tiles, the latency is equal to the time elapsed to accumulate a (1/k/sub 1/) portion of one image. In addition, a (2/k/sub 1/) potion of each image is buffered locally. The proposed hardware has been implemented on an FPGA and is part of a JPEG2000 compression system designed as a payload for a low Earth orbit (LEO) micro-satellite, which is due to be launched in August 2003.","PeriodicalId":173186,"journal":{"name":"2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128734725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Affine schemes in mesh-based video motion compensation 基于网格的视频运动补偿中的仿射算法
2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 2003-10-14 DOI: 10.1109/SIPS.2003.1235662
A. Utgikar, Wael Badawy, G. Seetharaman, M. Bayoumi
{"title":"Affine schemes in mesh-based video motion compensation","authors":"A. Utgikar, Wael Badawy, G. Seetharaman, M. Bayoumi","doi":"10.1109/SIPS.2003.1235662","DOIUrl":"https://doi.org/10.1109/SIPS.2003.1235662","url":null,"abstract":"We evaluate the performances of different implementations of affine transform in a motion compensation architecture based on a hierarchical adaptive structured mesh. The architecture predicts the next video frame using the reference frame, mesh code and mesh node motion vectors. It achieves significant reduction in describing the mesh topology by coding the splitting in recursive triangulation of the initial coarse geometry. It uses a memory serialization unit and one simple warping unit to map the hierarchical structure. The affine unit warps the texture of a patch at any level of hierarchical mesh independently. We compare shift-after-difference (SAD), lookup table (LUT) and naive implementations of the affine unit. Computing the affine transform using the multiplication-free SAD algorithm significantly reduces the complexity of the architecture. We establish from simulation results that our multiplication-free SAD affine computation requires far less power and area than other schemes. We discuss the limitations and advantages of different motion compensation schemes. Performance analysis shows that this scheme is suitable for video applications like MPEG and VRML.","PeriodicalId":173186,"journal":{"name":"2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127597889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Acoustic echo cancellation using blind source separation 基于盲源分离的声回波消除
2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 2003-10-14 DOI: 10.1109/SIPS.2003.1235676
Daesung Kim, Hun Choi, Hyundeok Bae
{"title":"Acoustic echo cancellation using blind source separation","authors":"Daesung Kim, Hun Choi, Hyundeok Bae","doi":"10.1109/SIPS.2003.1235676","DOIUrl":"https://doi.org/10.1109/SIPS.2003.1235676","url":null,"abstract":"We investigate an acoustic echo cancellation method using a blind source separation technique. In a hands-free mobile system, when the large acoustic noise picked up by the microphone is mixed with the echo, the echo cancellation system shows poor performance. We use a blind source separation algorithm to control the acoustic noise which has to be suppressed. The blind source separation algorithm separates the original echo signal from the observation signal which is mixed with acoustic noise. The separated echo signal is applied to the reference signal of the adaptive filter; this approach gives good performance of the adaptive algorithm for echo cancellation. Computer simulation results show the efficiency of the suggested method.","PeriodicalId":173186,"journal":{"name":"2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121778192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Systolic interpolation architectures for soft-decoding Reed-Solomon codes 软解码里德-所罗门码的收缩插值结构
2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 2003-10-14 DOI: 10.1109/SIPS.2003.1235648
A. Ahmed, Naresh R Shanbhag, R. Koetter
{"title":"Systolic interpolation architectures for soft-decoding Reed-Solomon codes","authors":"A. Ahmed, Naresh R Shanbhag, R. Koetter","doi":"10.1109/SIPS.2003.1235648","DOIUrl":"https://doi.org/10.1109/SIPS.2003.1235648","url":null,"abstract":"We present a systolic algorithm for performing interpolation, a computationally intensive kernel found in algebraic soft-decoding of Reed-Solomon codes. We reformulate the interpolation algorithm, resulting in a systolic interpolation algorithm, which can compute a reduced number of candidate polynomial coefficients. Using the dependence graph of the algorithm, we realize a low-latency interpolation architecture and a high-throughput interpolation architecture. These architectures are compared against previously: proposed architectures for an RS soft-decoder. We derive expressions for the latency of the systolic implementations and show that, for a reasonable hardware constraint, the low-latency systolic implementation reduces latency by 34% for a [255, 239] RS code. For the same code and hardware constraints, the high-throughput implementation, with a block pipelining depth of 5, increases throughput by 68%. In addition, the critical path of both the low-latency and the high-throughput implementation is smaller than that of previously proposed architectures.","PeriodicalId":173186,"journal":{"name":"2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134604278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
VLSI implementation of multiplier-free low power baseband filter for CDMA systems CDMA系统无乘法器低功率基带滤波器的VLSI实现
2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 2003-10-14 DOI: 10.1109/SIPS.2003.1235653
Y. Lian, Jianghong Yu
{"title":"VLSI implementation of multiplier-free low power baseband filter for CDMA systems","authors":"Y. Lian, Jianghong Yu","doi":"10.1109/SIPS.2003.1235653","DOIUrl":"https://doi.org/10.1109/SIPS.2003.1235653","url":null,"abstract":"A multiplier-free baseband filter is proposed for the low power VLSI implementation in a code division multiple access (CDMA) system. The new computational efficient filter structure is based on a novel prefilter structure involving a pair of even and odd length FIR filters with the same band edges. It is shown by example that the new structure not only achieves 45.8% savings in the number of multipliers, but also reduces the word length requirement for the coefficients of an IS-95 CDMA baseband filter. The VLSI implementation shows that the new structure reduces both the chip area and power consumption considerably compared with the direct-form implementation.","PeriodicalId":173186,"journal":{"name":"2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130875504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Recursive filtering on SIMD architectures SIMD架构上的递归过滤
2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 2003-10-14 DOI: 10.1109/SIPS.2003.1235680
R. Schaffer, M. Hosemann, R. Merker, G. Fettweis
{"title":"Recursive filtering on SIMD architectures","authors":"R. Schaffer, M. Hosemann, R. Merker, G. Fettweis","doi":"10.1109/SIPS.2003.1235680","DOIUrl":"https://doi.org/10.1109/SIPS.2003.1235680","url":null,"abstract":"Recursive filters are used frequently in digital signal processing. They can be implemented in dedicated hardware or in software on a digital signal processor (DSP). Software. solutions often are preferable for their speed of implementation and flexibility. However, contemporary DSPs are mostly not fast enough to perform filtering for high data-rates or large filters. A method to increase the computational power of a DSP without sacrificing efficiency is to use multiple processor elements controlled by the single-instruction multiple-data (SIMD) paradigm. The parallelization of recursive algorithms is difficult, because of the data dependencies. We use design methods for parallel processor arrays to realize implementations that can be used on a parallel DSP. Further, we focus on the partitioning of the algorithm so that the realization can be used for different architectures. Consequences for the architecture are also considered. The infinite impulse response (IIR) filter, the most familiar recursive filter, is used in the description of the design process.","PeriodicalId":173186,"journal":{"name":"2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127051134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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