2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682)最新文献_第7页

System-on-chip for communications: the dawn of ASIPs and the dusk of ASICs 片上系统通信:asic的黎明和asic的黄昏

2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 2003-08-27 DOI: 10.1109/SIPS.2003.1235634

H. Meyr

{"title":"System-on-chip for communications: the dawn of ASIPs and the dusk of ASICs","authors":"H. Meyr","doi":"10.1109/SIPS.2003.1235634","DOIUrl":"https://doi.org/10.1109/SIPS.2003.1235634","url":null,"abstract":"Summary form only given. ASIC designers have found that they can use less than half of the gates allowed by 90 nm technology. To make full use of the potential of semiconductor technology, a trend towards application specific SoCs will occur. A number of technical as well as economical reasons are responsible for this trend. We focus on SoCs for communication applications. The SoC can be viewed as software-definable, heterogeneous, multi-processor engine. A key role in the future will be played by ASIPs, which are jointly designed by algorithm and hardware architects. Moving from RT level ASIC design to coarse-grained ASIP building blocks is the logical result of a step up to a higher level of abstraction, comparable to the previous design revolution from gates to RTL. The design of ASIPs has become possible by new processor description languages, such as LISA, which contain the necessary information to synthesize automatically the instruction set and, at the same time, to generate the corresponding embedded software development environment including efficient HLL compilers. We conjecture that this fact will lead to a paradigm change in design methodology and will revolutionize the industry as it will enable system houses to use their IP optimally.","PeriodicalId":173186,"journal":{"name":"2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682)","volume":"305 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115445221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Hierarchical DSP architectural synthesis and scheduling solution for "IRIS" “IRIS”的DSP分层体系结构综合与调度解决方案

2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 2003-08-27 DOI: 10.1109/SIPS.2003.1235699

Y. Yi, Roger Francis Woods, R. Turner

引用次数: 4

AV codec prototype system using a low-power SPXK5SC DSP core AV编解码器原型系统采用低功耗SPXK5SC DSP核心

2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 2003-08-27 DOI: 10.1109/SIPS.2003.1235646

T. Kumura, N. Kayama, S. Shionoya, K. Kumagiri, T. Kusano, Minoru Yoshida, M. Ikekawa

{"title":"AV codec prototype system using a low-power SPXK5SC DSP core","authors":"T. Kumura, N. Kayama, S. Shionoya, K. Kumagiri, T. Kusano, Minoru Yoshida, M. Ikekawa","doi":"10.1109/SIPS.2003.1235646","DOIUrl":"https://doi.org/10.1109/SIPS.2003.1235646","url":null,"abstract":"The paper proposes a method for rapidly verifying and evaluating overall performance on real-time workloads of system LSIs integrated with SPXK5SC DSP cores. The SPXK5SC have been developed as a DSP core well-suited to system LSIs. Despite the fact that it is very important to evaluate the overall performance of target LSIs on real workloads before actual LSI fabrication, software simulators are too slow to deal with real workloads and full hardware prototyping is unable to respond well to design improvements. Therefore, we have developed a hardware emulation approach to be used on system LSIs integrated with an SPXK5SC DSP core in order to evaluate the overall performance of an audio/video codec on a target system. Our emulation system using a DSP core TEG (test element group), which has a bus interface, and an FPGA should be suitable for overall system evaluation on real-time workloads as well as architectural investigation. We discuss the use of the emulation system in evaluating performance during AV codec execution. An architecture design based on our emulation system is also described.","PeriodicalId":173186,"journal":{"name":"2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131655644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) 2003年IEEE信号处理系统研讨会。No.03TH8682)

2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2003.1235630

引用次数: 0

VLSI architecture for discrete wavelet transform based on B-spline factorization 基于b样条分解的离散小波变换VLSI结构

2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2003.1235694

Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen

引用次数: 20

A low power algorithm for sparse system identification using cross correlation 一种基于互相关的低功耗稀疏系统辨识算法

2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2003.1235637

F. O'Regan, C. Heneghan

引用次数: 3

Methodology for refinement and optimization of dynamic memory management for embedded systems in multimedia applications 多媒体应用中嵌入式系统动态存储器管理的改进和优化方法

2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2003.1235698

M. Leeman, G. Deconinck, V. De Florio, David Atienza Alonso, J. Mendias, C. Ykman, F. Catthoor, R. Lauwereins

{"title":"Methodology for refinement and optimization of dynamic memory management for embedded systems in multimedia applications","authors":"M. Leeman, G. Deconinck, V. De Florio, David Atienza Alonso, J. Mendias, C. Ykman, F. Catthoor, R. Lauwereins","doi":"10.1109/SIPS.2003.1235698","DOIUrl":"https://doi.org/10.1109/SIPS.2003.1235698","url":null,"abstract":"In multimedia applications, run-time memory management support has to allow real-time memory de/allocation, retrieving and processing of data. Thus, its implementation must be designed to combine high speed, low power, large data storage capacity and a high memory bandwidth. We assess the performance of our new system-level exploration methodology to optimize the memory management of typical multimedia applications in an extensively used 3D image reconstruction system (Pollefeys, M. et al, 1998; Cosmas, J. et al, 2002). This methodology is based on an analysis of the number of memory accesses, normalized memory use and energy estimations for the system studied. This results in an improvement in the normalized memory footprint of up to 44.2% and in the estimated energy dissipation of up to 22.6% over conventional static memory implementations in an optimized version of the driver application. Finally, our final version is able to scale perfectly the memory consumed in the system for a wide range of input parameters, whereas the statically optimized version is unable to do this.","PeriodicalId":173186,"journal":{"name":"2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129694923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10