Hierarchical DSP architectural synthesis and scheduling solution for "IRIS"

Y. Yi, Roger Francis Woods, R. Turner
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引用次数: 4

Abstract

Increasingly, DSP design flows need to cope with a hierarchy involving complex components rather than simple blocks such as multipliers. The paper outlines some of the challenges of such a design approach using a wave digital filter example. The paper outlines how an "in-house" architectural synthesis tool, IRIS, has been modified to synthesize such structures. An extended MARS (Minnesota architecture synthesis) scheduling algorithm for hierarchical scheduling is also proposed for reducing the area of the synthesized circuit.
“IRIS”的DSP分层体系结构综合与调度解决方案
越来越多的DSP设计流程需要处理涉及复杂组件的层次结构,而不是像乘数器这样的简单模块。本文用一个波数字滤波器的例子概述了这种设计方法的一些挑战。本文概述了如何修改“内部”建筑综合工具IRIS来综合此类结构。为了减小合成电路的面积,提出了一种适用于分层调度的扩展MARS (Minnesota architecture synthesis)调度算法。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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