AV codec prototype system using a low-power SPXK5SC DSP core

2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 2003-08-27 DOI:10.1109/SIPS.2003.1235646

T. Kumura, N. Kayama, S. Shionoya, K. Kumagiri, T. Kusano, Minoru Yoshida, M. Ikekawa

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Abstract

The paper proposes a method for rapidly verifying and evaluating overall performance on real-time workloads of system LSIs integrated with SPXK5SC DSP cores. The SPXK5SC have been developed as a DSP core well-suited to system LSIs. Despite the fact that it is very important to evaluate the overall performance of target LSIs on real workloads before actual LSI fabrication, software simulators are too slow to deal with real workloads and full hardware prototyping is unable to respond well to design improvements. Therefore, we have developed a hardware emulation approach to be used on system LSIs integrated with an SPXK5SC DSP core in order to evaluate the overall performance of an audio/video codec on a target system. Our emulation system using a DSP core TEG (test element group), which has a bus interface, and an FPGA should be suitable for overall system evaluation on real-time workloads as well as architectural investigation. We discuss the use of the emulation system in evaluating performance during AV codec execution. An architecture design based on our emulation system is also described.

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AV编解码器原型系统采用低功耗SPXK5SC DSP核心

本文提出了一种在实时工作负载下快速验证和评估集成了SPXK5SC DSP内核的系统lsi整体性能的方法。SPXK5SC是一种非常适合系统lsi的DSP核心。尽管在实际LSI制造之前评估目标LSI在实际工作负载上的整体性能非常重要，但软件模拟器太慢，无法处理实际工作负载，并且完整的硬件原型无法很好地响应设计改进。因此，我们开发了一种硬件仿真方法，用于与SPXK5SC DSP核心集成的系统lsi，以评估目标系统上音频/视频编解码器的整体性能。我们的仿真系统使用一个DSP核心TEG(测试元件组)，它有一个总线接口，和一个FPGA应该适合于对实时工作负载的整体系统评估以及架构调查。我们讨论了仿真系统在AV编解码器执行过程中评估性能的使用。本文还介绍了基于仿真系统的体系结构设计。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682)

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