2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682)最新文献_第2页

A mixed QoS SDRAM controller for FPGA-based high-end image processing 基于fpga的高端图像处理混合QoS SDRAM控制器

2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 2003-10-14 DOI: 10.1109/SIPS.2003.1235690

S. Heithecker, A. do Carmo Lucas, R. Ernst

引用次数: 33

An efficient implementation of hierarchical image coding 一个有效的实现分层图像编码

2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 2003-10-14 DOI: 10.1109/SIPS.2003.1235697

J. Lee, N. Vijaykrishnan, M. J. Irwin, R. Chandramouli

引用次数: 0

Implementation of complex-arithmetic heterodyne filter 复算法外差滤波器的实现

2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 2003-10-14 DOI: 10.1109/SIPS.2003.1235674

M. Soderstrand, A. Azam, D. Sasidaran, K. Nelson

引用次数: 3

A novel vario-power architecture of motion estimation using a content based subsample algorithm 一种新的基于内容的子样本算法的运动估计的变功率结构

2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 2003-10-14 DOI: 10.1109/SIPS.2003.1235669

Hsien-Wen Cheng, Lan-Rong Dung

引用次数: 0

Efficient IMDCT core designs for audio signal processing 音频信号处理的高效IMDCT核心设计

2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 2003-10-14 DOI: 10.1109/SIPS.2003.1235682

Po-Sheng Wu, Yin-Tsung Hwan

引用次数: 8

VLSI implementation of invisible digital watermarking algorithms towards the development of a secure JPEG encoder 采用VLSI实现不可见数字水印算法，开发一种安全的JPEG编码器

2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 2003-10-14 DOI: 10.1109/SIPS.2003.1235666

S. Mohanty, Nagarajan Ranganathan, R. Namballa

引用次数: 69

Viterbi decoding on a coprocessor architecture with vector parallelism 具有向量并行性的协处理器结构上的维特比解码

2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 2003-10-14 DOI: 10.1109/SIPS.2003.1235692

N. Engin, K. van Berkel

引用次数: 5

Reconfigurable discrete wavelet transform architecture for advanced multimedia systems 用于高级多媒体系统的可重构离散小波变换体系结构

2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 2003-10-14 DOI: 10.1109/SIPS.2003.1235658

Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen

{"title":"Reconfigurable discrete wavelet transform architecture for advanced multimedia systems","authors":"Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen","doi":"10.1109/SIPS.2003.1235658","DOIUrl":"https://doi.org/10.1109/SIPS.2003.1235658","url":null,"abstract":"A novel reconfigurable discrete wavelet transform architecture is proposed to meet the diverse computing requirements of advanced multimedia systems. The proposed architecture mainly consists of a reconfigurable processing element array and a reconfigurable address generator, featuring a dynamically reconfigurable capability where the wavelet filter kernels and wavelet decomposition structures can be reconfigured at run-time with little overhead. The lifting-based reconfigurable processing element array possesses better computational efficiency than a convolution-based architecture, and a systematic design method is provided to generate the hardware configurations of different wavelet filter kernels for it. The reconfigurable address generator handles flexible address generation for data I/O access in different wavelet decomposition structures. A prototyping chip has been fabricated by the TSMC 0.35 /spl mu/m 1P4M CMOS process, and, at 50 MHz, it can achieve at most 100 Mpixel/sec transform throughput, proving it to be a universal and extremely flexible computing engine for advanced multimedia systems.","PeriodicalId":173186,"journal":{"name":"2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123867295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

An MPEG-4 facial animation parameters generation system 一个MPEG-4面部动画参数生成系统

2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 2003-10-14 DOI: 10.1109/SIPS.2003.1235664

G. Hovden, N. Ling

引用次数: 2

High-performance and energy-efficient heterogeneous subword parallel instructions 高性能和节能异构子词并行指令

2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) Pub Date : 2003-10-14 DOI: 10.1109/SIPS.2003.1235647

Jong-Myon Kim, D. S. Wills

{"title":"High-performance and energy-efficient heterogeneous subword parallel instructions","authors":"Jong-Myon Kim, D. S. Wills","doi":"10.1109/SIPS.2003.1235647","DOIUrl":"https://doi.org/10.1109/SIPS.2003.1235647","url":null,"abstract":"High instruction throughput and energy efficiency are becoming increasingly important design requirements for embedded and mobile computing systems. The paper presents the quantized color pack extension (QCPX) ISA to improve execution performance of multimedia processing applications on programmable superscalar processors while reducing the energy consumption for these applications. QCPX exploits parallelism within the color space representation (YCbCr - luminance-chrominance) in addition to generic subword parallelism exploited by existing multimedia instruction set extensions (e.g., MMX, SSE, MDMX). We evaluate the performance (execution time in cycles) and energy consumption using QCPX on a media benchmark suite that includes vector median filter, scalar median filter, edge detection, and vector quantization. Our experimental results indicate that a 32-bit QCPX version achieves speedups ranging from 205% to 562% compared with that of a 32-bit baseline RISC version and 90% to 100% over the 32-bit MDMX-like version on identically configured, dynamically scheduled ILP superscalar processors. In addition, the QCPX version reduces the energy consumption from 69% to 83% over the baseline version and 47% to 50% over the MDMX-like version due to the significant reduction of executed instructions and cache accesses.","PeriodicalId":173186,"journal":{"name":"2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125395011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0