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2008 International Symposium on System-on-Chip最新文献

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UML profile for estimating application Worst Case Execution Time on System-on-Chip 用于在片上系统上估计应用程序最坏情况执行时间的UML概要文件
2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694865
Fateh Boutekkouk, S. Bilavarn, M. Auguin, Mohammed Benmohammed
{"title":"UML profile for estimating application Worst Case Execution Time on System-on-Chip","authors":"Fateh Boutekkouk, S. Bilavarn, M. Auguin, Mohammed Benmohammed","doi":"10.1109/ISSOC.2008.4694865","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694865","url":null,"abstract":"Systems-on-chip (SOC) design is confronted with the problem of the so-called productivity gap. In order to cope with this problem, authors emphasize on using the unified modeling language (UML) as a system level language, so higher level of abstraction is achieved. In this context, we present a UML profile and a methodology for estimating application worst case execution time (WCET) on SOC. The proposed profile allows the designer to express hierarchy among application tasks, and most of parallelism forms that exist in typical embedded applications such as task parallelism, pipelining, and data parallelism, while making control and communication over tasks explicit. In order to estimate application WCET, the hardware platform on which application is mapped on, should be abstracted too. Consequently, each hardware component is parameterized by a set of parameters matching the abstraction level of the application. A particularity of our flow is that it starts by establishing a sequential object model using UML sequence diagram, from which a task-level model is extracted. We think that the sequential model is strongly preferred from the system designerpsilas perspective for two reasons. First, because it facilitates the modelling task relieving the designer of the burden of concurrency modelling. Secondly, starting from an existing sequential model (e.g. legacy C code) which is generally considered as the reference model, we can then parallelize it, and explore the design space. We show how we have used our profile for H264 decoder modeling.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116753204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Specification of GNSS application for multiprocessor platform 多处理器平台GNSS应用规范
2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694866
H. Hurskainen, J. Raasakka, J. Nurmi
{"title":"Specification of GNSS application for multiprocessor platform","authors":"H. Hurskainen, J. Raasakka, J. Nurmi","doi":"10.1109/ISSOC.2008.4694866","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694866","url":null,"abstract":"In this paper we present a satellite navigation application for a multiprocessor platform. We give a preliminary description to the multiprocessor platform with an introduction to the project where it will be designed and implemented to a fabric die. The platform contains a matrix of processing tiles, connected together via a Network-on-Chip. The satellite navigation application is one of the streaming applications designed to be executed on this platform. Detailed descriptions of the signal processing functions for acquiring and tracking the satellite signals for navigation are given. The estimations of their requirements for computational complexity, measured as multiply-accumulate counts, are also presented in this paper. The results indicate that one processing tile on the platform could barely perform the required signal processing functions and thus more tiles are preferred for a better user experience. This work is carried out in the EU FP7 project called CRISP (Cutting edge Reconfigurable ICs for Stream Processing).","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132274138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
TLMCO-simulation for an open source MPSOC platform under STARSoC environment STARSoC环境下开源MPSOC平台的tlmco仿真
2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694862
S. Boukhechem, E. Bourennane
{"title":"TLMCO-simulation for an open source MPSOC platform under STARSoC environment","authors":"S. Boukhechem, E. Bourennane","doi":"10.1109/ISSOC.2008.4694862","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694862","url":null,"abstract":"In the last decade, the embedded systems become more and more complex. This complexity is due to the fact that these systems contain more heterogeneous hardware and software components (CPUpsilas, DSP, IP, etc.). Such systems called multiprocessor-on-chip (MPSoC) require new design approaches in order to satisfy several constraints, verification time, cost and time to market.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115967288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low noise amplifier architecture analysis for UWB system 超宽带系统的低噪声放大器结构分析
2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694890
Peng Wang, F. Jonsson, Dian Zhou, Lirong Zheng
{"title":"Low noise amplifier architecture analysis for UWB system","authors":"Peng Wang, F. Jonsson, Dian Zhou, Lirong Zheng","doi":"10.1109/ISSOC.2008.4694890","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694890","url":null,"abstract":"This paper analyzes the architecture of wideband low noise amplifier (LNA) for multi-band orthogonal frequency division multiplexing modulation (MB-OFDM) ultra-wideband (UWB) system. Noise matching and input impedance matching are compared among different LNA architectures. Power consumption and area for different kinds of LNA architectures are also compared through the figure of merit (FOM).","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123797966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Using soft processors for component design in SOC: A case-study of timers 在SOC中使用软处理器进行元件设计:以计时器为例
2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694873
M. Ortiz, M. Brox, F. J. Quiles-Latorre, A. Gersnoviez, C. D. Moreno-Moreno, M. Montijano
{"title":"Using soft processors for component design in SOC: A case-study of timers","authors":"M. Ortiz, M. Brox, F. J. Quiles-Latorre, A. Gersnoviez, C. D. Moreno-Moreno, M. Montijano","doi":"10.1109/ISSOC.2008.4694873","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694873","url":null,"abstract":"System on Chip (SOC) could be considered as a very useful alternative in the design of real-time systems, especially due to the possibility of integrating several processors in just one FPGA. This strategy enables the use of soft processors to design the systempsilas components, which have traditionally been developed by hardware. In this paper we study a HW/SW codesign of a timer pool for its use in SOC, which is constructed by a Picoblaze soft processor. Our approach offers a novel alternative among hardware and software timers that increases the overall system performance, and achieves a higher precision than software timers with a considerable reduction in cost and area occupied.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126162584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 65nm CMOS down-sampling micromixer with enhanced DC current capability 具有增强直流电流能力的65纳米CMOS下采样微混频器
2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694857
K. Schweiger, H. Zimmermann
{"title":"A 65nm CMOS down-sampling micromixer with enhanced DC current capability","authors":"K. Schweiger, H. Zimmermann","doi":"10.1109/ISSOC.2008.4694857","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694857","url":null,"abstract":"This paper presents a low power CMOS down sampling micromixer in 65nm with an improved input stage. It is able to handle a superimposed DC current on the input port without degrading circuit performance. The mixer was fabricated in a triple-well process. A conversion gain of 17dB is achieved while only consuming 780muW from a 1.2V voltage supply up to a 3dB clock frequency of 600MHz. The gain decreases for 3dB at a superimposed DC current of 210muA. The 1dB compression point and IIP3 are measured to be -22.7dBm and -16dBm, respectively.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121546588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Configuring Smart Objects over cognitive radio 通过认知无线电配置智能对象
2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694871
Karri Nikunen, Hannu Heusala, Jeppe Komulainen
{"title":"Configuring Smart Objects over cognitive radio","authors":"Karri Nikunen, Hannu Heusala, Jeppe Komulainen","doi":"10.1109/ISSOC.2008.4694871","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694871","url":null,"abstract":"The most promising application of field programmable gate arrays (FPGA) is reconfigurable computing, which gives basis for prototyping a swarm intelligence and the behavior of smart objects. With different configurations, the functionality of an FPGA can change different modular units of smart objects. With a swarm of these FPGA-based objects, it is possible to take advantage of a new kind of data processing method: cognitive computing. The use of cognitive radio makes this technology more dependable. These smart objects have to be developed to a level where they communicate safely before any bigger evolution can happen. So, how do we reconfigure these small smart objects safely over a wireless network? This paper introduces an implement prototype which enables the safer reconfiguration of hardware logic over a wireless radio link by using frequency hopping and by searching for available noiseless channels.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127098775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High resolution flash time-to-digital converter with sub-picosecond measurement capabilities 具有亚皮秒测量能力的高分辨率闪光时间-数字转换器
2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694882
N. Minas, D. Kinniment, G. Russell, A. Yakovlev
{"title":"High resolution flash time-to-digital converter with sub-picosecond measurement capabilities","authors":"N. Minas, D. Kinniment, G. Russell, A. Yakovlev","doi":"10.1109/ISSOC.2008.4694882","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694882","url":null,"abstract":"The paper presents a flash TDC implemented in a UMC 0.13 um technology node. The maximum resolution of 0.6 ps and a dynamic range of plusmn17 ps makes it ideal for measuring set-up and hold time violations and quantifying clock jitter. The method proposed has the effect of reducing the errors introduced by noise and process variations by a factor of two over present techniques. A novel method for overcoming the effects of process variability by counting the number of high outputs is also presented.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129161144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A two-phase return-to-zero (RZ) asynchronous transceiver circuit for pipe-lined SoC interconnects 一种用于管道式SoC互连的两相归零(RZ)异步收发器电路
2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694881
M. Elrabaa
{"title":"A two-phase return-to-zero (RZ) asynchronous transceiver circuit for pipe-lined SoC interconnects","authors":"M. Elrabaa","doi":"10.1109/ISSOC.2008.4694881","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694881","url":null,"abstract":"A new delay-insensitive two-phase asynchronous handshaking protocol has been developed. The new protocol utilizes return to zero data format which simplifies communication circuits design significantly. Robust transceiver circuitry that implement this protocol have been developed and simulated using a 0.13mum, 1.2V technology to verify their performance.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130271344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
FPGA implementation of a 2G fibre channel link encryptor with authenticated encryption mode GCM 采用认证加密模式GCM的2G光纤通道链路加密器的FPGA实现
2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694859
L. Henzen, F. Carbognani, N. Felber, W. Fichtner
{"title":"FPGA implementation of a 2G fibre channel link encryptor with authenticated encryption mode GCM","authors":"L. Henzen, F. Carbognani, N. Felber, W. Fichtner","doi":"10.1109/ISSOC.2008.4694859","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694859","url":null,"abstract":"The Galois/counter mode (GCM) algorithm enables fast encryption combined with per-packet message authentication. This paper presents an FPGA implementation of a complete bidirectional 2 Gbps fibre channel link encryptor hosting two area-optimized GCM cores for concurrent authenticated encryption and decryption. The proposed architecture fits into one Xilinx Virtex-4 device. Measurements in a working network link point out that per-packet authentication results in a speed decrease up to 20% of the channel capacity for a reference frame length of 256 bits. Two methods of frame encryption are investigated to reduce the required GCM overhead and to exploit different network configurations.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130765584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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