A 65nm CMOS down-sampling micromixer with enhanced DC current capability

K. Schweiger, H. Zimmermann
{"title":"A 65nm CMOS down-sampling micromixer with enhanced DC current capability","authors":"K. Schweiger, H. Zimmermann","doi":"10.1109/ISSOC.2008.4694857","DOIUrl":null,"url":null,"abstract":"This paper presents a low power CMOS down sampling micromixer in 65nm with an improved input stage. It is able to handle a superimposed DC current on the input port without degrading circuit performance. The mixer was fabricated in a triple-well process. A conversion gain of 17dB is achieved while only consuming 780muW from a 1.2V voltage supply up to a 3dB clock frequency of 600MHz. The gain decreases for 3dB at a superimposed DC current of 210muA. The 1dB compression point and IIP3 are measured to be -22.7dBm and -16dBm, respectively.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"135 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 International Symposium on System-on-Chip","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSOC.2008.4694857","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

This paper presents a low power CMOS down sampling micromixer in 65nm with an improved input stage. It is able to handle a superimposed DC current on the input port without degrading circuit performance. The mixer was fabricated in a triple-well process. A conversion gain of 17dB is achieved while only consuming 780muW from a 1.2V voltage supply up to a 3dB clock frequency of 600MHz. The gain decreases for 3dB at a superimposed DC current of 210muA. The 1dB compression point and IIP3 are measured to be -22.7dBm and -16dBm, respectively.
具有增强直流电流能力的65纳米CMOS下采样微混频器
本文提出了一种改进了输入级的65nm低功耗CMOS下采样微混频器。它能够在不降低电路性能的情况下处理输入端口上的叠加直流电流。混合器是用三孔工艺制造的。在3dB时钟频率为600MHz时,在1.2V电压电源仅消耗780muW的情况下实现17dB的转换增益。当叠加直流电流为210muA时,增益降低3dB。1dB压缩点和IIP3分别测量为-22.7dBm和-16dBm。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信